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Message-ID: <20250507-invisible-nice-ostrich-fb9c7b@kuoka>
Date: Wed, 7 May 2025 07:12:38 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Cc: vkoul@...nel.org, kishon@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, dmitry.baryshkov@...aro.org,
neil.armstrong@...aro.org, abel.vesa@...aro.org, manivannan.sadhasivam@...aro.org,
lpieralisi@...nel.org, kw@...ux.com, bhelgaas@...gle.com, andersson@...nel.org,
konradybcio@...nel.org, linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
quic_qianyu@...cinc.com, quic_krichai@...cinc.com, quic_vbadigan@...cinc.com
Subject: Re: [PATCH v4 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy:
Update pcie phy bindings for QCS615
On Wed, May 07, 2025 at 11:15:55AM GMT, Ziyue Zhang wrote:
> QCS615 pcie phy only use 5 clocks, which are aux, cfg_ahb, ref,
> ref_gen, pipe. So move "qcom,qcs615-qmp-gen3x1-pcie-phy" compatible
> from 6 clocks' list to 5 clocks' list.
Same for QCS8300 patchset: what changed in the hardware that now it uses
different amount of clocks than before?
Best regards,
Krzysztof
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