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Message-ID: <20250507-astute-realistic-ferret-bcdfce@kuoka>
Date: Wed, 7 May 2025 07:17:08 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Cc: vkoul@...nel.org, kishon@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, dmitry.baryshkov@...aro.org,
neil.armstrong@...aro.org, abel.vesa@...aro.org, manivannan.sadhasivam@...aro.org,
lpieralisi@...nel.org, kw@...ux.com, bhelgaas@...gle.com, andersson@...nel.org,
konradybcio@...nel.org, linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
quic_qianyu@...cinc.com, quic_krichai@...cinc.com, quic_vbadigan@...cinc.com
Subject: Re: [PATCH v4 2/5] dt-bindings: PCI: qcom: Document the QCS615 PCIe
Controller
On Wed, May 07, 2025 at 11:15:56AM GMT, Ziyue Zhang wrote:
> From: Krishna chaitanya chundru <quic_krichai@...cinc.com>
>
> Add dedicated schema for the PCIe controllers found on QCS615.
> Due to qcs615's clock-names do not match any of the existing
> dt-bindings, a new compatible for qcs615 is needed.
Other bindings for QCS615 were not finished, so I have doubts this is
done as well. Send your bindings once you finish them.
...
> +properties:
> + compatible:
> + const: qcom,qcs615-pcie
> +
> + reg:
> + minItems: 6
> + maxItems: 6
> +
> + reg-names:
> + items:
> + - const: parf # Qualcomm specific registers
> + - const: dbi # DesignWare PCIe registers
> + - const: elbi # External local bus interface registers
> + - const: atu # ATU address space
> + - const: config # PCIe configuration space
> + - const: mhi # MHI registers
> +
> + clocks:
> + minItems: 5
Drop or use correct value - 6. I don't understand why this changed and
nothing in changelog explains this.
Best regards,
Krzysztof
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