linux-kernel - Re: [PATCH v4 5/5] PCI: qcom: Add support for QCS615 SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20250507-competent-meek-prawn-72badf@kuoka>
Date: Wed, 7 May 2025 07:18:33 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Cc: vkoul@...nel.org, kishon@...nel.org, robh@...nel.org, 
	krzk+dt@...nel.org, conor+dt@...nel.org, dmitry.baryshkov@...aro.org, 
	neil.armstrong@...aro.org, abel.vesa@...aro.org, manivannan.sadhasivam@...aro.org, 
	lpieralisi@...nel.org, kw@...ux.com, bhelgaas@...gle.com, andersson@...nel.org, 
	konradybcio@...nel.org, linux-phy@...ts.infradead.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org, 
	quic_qianyu@...cinc.com, quic_krichai@...cinc.com, quic_vbadigan@...cinc.com
Subject: Re: [PATCH v4 5/5] PCI: qcom: Add support for QCS615 SoC

On Wed, May 07, 2025 at 11:15:59AM GMT, Ziyue Zhang wrote:
> Add the compatible and the driver data for QCS615 PCIe controller.
> There is only one controller instance found on this platform, which
> is capable of up to 8.0GT/s.
> The version of the controller is 1.38.0 which is compatible with 1.9.0
> config.
> 
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index dc98ae63362d..0ed934b0d1be 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1862,6 +1862,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>  	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
>  	{ .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
>  	{ .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
> +	{ .compatible = "qcom,qcs615-pcie", .data = &cfg_1_9_0 },

Why? It's compatible with other entries, so why adding redundant entry
here?

Best regards,
Krzysztof