lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <045701dbc153$3aa85bc0$aff91340$@samsung.com>
Date: Sat, 10 May 2025 07:58:31 +0530
From: "Alim Akhtar" <alim.akhtar@...sung.com>
To: "'Pritam Manohar Sutar'" <pritam.sutar@...sung.com>, <krzk@...nel.org>,
	<s.nawrocki@...sung.com>, <cw00.choi@...sung.com>,
	<mturquette@...libre.com>, <sboyd@...nel.org>, <sunyeal.hong@...sung.com>
Cc: <linux-samsung-soc@...r.kernel.org>, <linux-clk@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
	<rosa.pila@...sung.com>, <dev.tailor@...sung.com>, <faraz.ata@...sung.com>,
	"'stable'" <stable@...nel.org>
Subject: RE: [PATCH v2] clk: samsung: correct clock summary for hsi1 block

Hi Pritam

> -----Original Message-----
> From: Pritam Manohar Sutar <pritam.sutar@...sung.com>
> Sent: Tuesday, May 6, 2025 1:32 PM
> To: krzk@...nel.org; s.nawrocki@...sung.com; cw00.choi@...sung.com;
> alim.akhtar@...sung.com; mturquette@...libre.com; sboyd@...nel.org;
> sunyeal.hong@...sung.com
> Cc: linux-samsung-soc@...r.kernel.org; linux-clk@...r.kernel.org; linux-
> arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
> rosa.pila@...sung.com; dev.tailor@...sung.com;
> faraz.ata@...sung.com; Pritam Manohar Sutar
> <pritam.sutar@...sung.com>; stable <stable@...nel.org>
> Subject: [PATCH v2] clk: samsung: correct clock summary for hsi1 block
> 
> clk_summary shows wrong value for "mout_hsi1_usbdrd_user".
> It shows 400Mhz instead of 40Mhz as below.
> 
> dout_shared2_div4           1 1 0 400000000 0 0 50000 Y ...
>   mout_hsi1_usbdrd_user     0 0 0 400000000 0 0 50000 Y ...
>     dout_clkcmu_hsi1_usbdrd 0 0 0 40000000  0 0 50000 Y ...
> 
> Correct the clk_tree by adding correct clock parent for
> "mout_hsi1_usbdrd_user".
> 
> Post this change, clk_summary shows correct value.
> 
> dout_shared2_div4           1 1 0 400000000 0 0 50000 Y ...
>   mout_clkcmu_hsi1_usbdrd   0 0 0 400000000 0 0 50000 Y ...
>     dout_clkcmu_hsi1_usbdrd 0 0 0 40000000  0 0 50000 Y ...
>       mout_hsi1_usbdrd_user 0 0 0 40000000  0 0 50000 Y ...
> 
> Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto
> v920 SoC")
> Cc: stable <stable@...nel.org>
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@...sung.com>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@...sung.com>


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ