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Message-ID: <7eaaea13-a61d-4a1d-a539-6bfb70bb2fc0@kernel.org>
Date: Mon, 12 May 2025 08:29:43 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Pritam Manohar Sutar <pritam.sutar@...sung.com>, s.nawrocki@...sung.com,
cw00.choi@...sung.com, alim.akhtar@...sung.com, mturquette@...libre.com,
sboyd@...nel.org, sunyeal.hong@...sung.com
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
rosa.pila@...sung.com, dev.tailor@...sung.com, faraz.ata@...sung.com,
stable <stable@...nel.org>
Subject: Re: [PATCH v2] clk: samsung: correct clock summary for hsi1 block
On 06/05/2025 10:01, Pritam Manohar Sutar wrote:
> clk_summary shows wrong value for "mout_hsi1_usbdrd_user".
> It shows 400Mhz instead of 40Mhz as below.
>
> dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
> mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ...
> dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
>
> Correct the clk_tree by adding correct clock parent for
> "mout_hsi1_usbdrd_user".
>
> Post this change, clk_summary shows correct value.
>
> dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
> mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ...
> dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
> mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ...
>
> Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto v920 SoC")
> Cc: stable <stable@...nel.org>
Run checkpatch BEFORE you send the patches.
WARNING: Invalid email format for stable: 'stable <stable@...nel.org>',
prefer 'stable@...nel.org'
Best regards,
Krzysztof
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