linux-kernel - Re: [PATCH V6 3/5] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

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Message-ID: <20250511133055.54869b61@jic23-huawei>
Date: Sun, 11 May 2025 13:30:55 +0100
From: Jonathan Cameron <jic23@...nel.org>
To: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
Cc: robh@...nel.org, krzysztof.kozlowski@...aro.org, krzk+dt@...nel.org,
 conor+dt@...nel.org, agross@...nel.org, andersson@...nel.org,
 lumag@...nel.org, dmitry.baryshkov@....qualcomm.com,
 konradybcio@...nel.org, daniel.lezcano@...aro.org, sboyd@...nel.org,
 amitk@...nel.org, thara.gopinath@...il.com, lee@...nel.org,
 rafael@...nel.org, subbaraman.narayanamurthy@....qualcomm.com,
 david.collins@....qualcomm.com, anjelique.melendez@....qualcomm.com,
 quic_kamalw@...cinc.com, rui.zhang@...el.com, lukasz.luba@....com,
 devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
 linux-iio@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-pm@...r.kernel.org, cros-qcom-dts-watchers@...omium.org,
 quic_skakitap@...cinc.com, neil.armstrong@...aro.org,
 stephan.gerhold@...aro.org
Subject: Re: [PATCH V6 3/5] dt-bindings: iio: adc: Add support for QCOM
 PMIC5 Gen3 ADC

On Fri,  9 May 2025 16:39:57 +0530
Jishnu Prakash <jishnu.prakash@....qualcomm.com> wrote:

> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
> 
> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> going through PBS(Programmable Boot Sequence) firmware through a single
> register interface. This interface is implemented on SDAM (Shared
> Direct Access Memory) peripherals on the master PMIC PMK8550 rather
> than a dedicated ADC peripheral.
> 
> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
> channels and virtual channels (combination of ADC channel number and
> PMIC SID number) per PMIC, to be used by clients of this device.
> 
> Signed-off-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>

This looks fine to me.  The dependencies on previous two patches
make this a little tricky to handle though. I don't like splitting the
path the binding and the driver take to upstream but in this case
we probably either have to merge them in different cycles or this
needs to go with those code movement patches.  It looked like an
immutable branch would be very messy given additions that the 1st patch
touches probably mean an immutable would have to include a lot of
stuff that is queued up in the Qualcomm SoC tree.

If the rest of the necessary reviews turn up this cycle to get everything
in this cycle merge (seems unlikely) then I don't thing routing this
via the SoC tree will be a problem.

To enable that

Acked-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>

I suspect given timing best we can hope for is patches 1 and 2 go
via the SoC tree asap and we deal with the rest at start of next cycle
but I like to be optimistic :)

Jonathan