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Message-Id: <20250511172732.1467671-1-da@libre.computer>
Date: Sun, 11 May 2025 13:27:32 -0400
From: Da Xue <da@...re.computer>
To: Neil Armstrong <neil.armstrong@...aro.org>,
Jerome Brunet <jbrunet@...libre.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Kevin Hilman <khilman@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: Da Xue <da@...re.computer>,
stable@...r.kernel.org,
linux-amlogic@...ts.infradead.org,
linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] clk: meson-g12a: fix missing spicc clks to clk_sel
HHI_SPICC_CLK_CNTL bits 25:23 controls spicc clk_sel.
It is missing fclk_div 2 and gp0_pll which causes the spicc module to
output the incorrect clocks for spicc sclk at 2.5x the expected rate.
Add the missing clocks resolves this.
Cc: <stable@...r.kernel.org> # 6.1.x: a18c8e0: clk: meson: g12a: add
Signed-off-by: Da Xue <da@...re.computer>
---
drivers/clk/meson/g12a.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 4f92b83965d5a..892862bf39996 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -4099,8 +4099,10 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = {
{ .hw = &g12a_clk81.hw },
{ .hw = &g12a_fclk_div4.hw },
{ .hw = &g12a_fclk_div3.hw },
+ { .hw = &g12a_fclk_div2.hw },
{ .hw = &g12a_fclk_div5.hw },
{ .hw = &g12a_fclk_div7.hw },
+ { .hw = &g12a_gp0_pll.hw, },
};
static struct clk_regmap g12a_spicc0_sclk_sel = {
--
2.39.5
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