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Message-ID: <d67d893e-9c7e-487e-a14b-419a7cdc6158@linux.dev>
Date: Mon, 12 May 2025 11:56:28 -0400
From: Sean Anderson <sean.anderson@...ux.dev>
To: Mark Rutland <mark.rutland@....com>
Cc: Sudeep Holla <sudeep.holla@....com>,
Catalin Marinas <catalin.marinas@....com>,
linux-arm-kernel@...ts.infradead.org, Radu Rendec <rrendec@...hat.com>,
Will Deacon <will@...nel.org>,
Thomas Weißschuh <thomas.weissschuh@...utronix.de>,
Thomas Gleixner <tglx@...utronix.de>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: cacheinfo: Report cache sets, ways, and line size
On 5/12/25 11:36, Mark Rutland wrote:
> On Mon, May 12, 2025 at 11:28:36AM -0400, Sean Anderson wrote:
>> On 5/10/25 03:04, Sudeep Holla wrote:
>> > On Fri, May 09, 2025 at 07:37:35PM -0400, Sean Anderson wrote:
>> >> Cache geometry is exposed through the Cache Size ID register. There is
>> >> one register for each cache, and they are selected through the Cache
>> >> Size Selection register. If FEAT_CCIDX is implemented, the layout of
>> >> CCSIDR changes to allow a larger number of sets and ways.
>> >>
>> >
>> > Please refer
>> > Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing")
>> >
>>
>> | The CCSIDR_EL1.{NumSets,Associativity,LineSize} fields are only for use
>> | in conjunction with set/way cache maintenance and are not guaranteed to
>> | represent the actual microarchitectural features of a design.
>> |
>> | The architecture explicitly states:
>> |
>> | | You cannot make any inference about the actual sizes of caches based
>> | | on these parameters.
>>
>> However, on many cores (A53, A72, and surely others that I haven't
>> checked) these *do* expose the actual microarchitectural features of the
>> design. Maybe a whitelist would be suitable.
>
> Then we have to maintain a whitelist forever,
There's no maintenance involved. The silicon is already fabbed, so it's
not like it's going to change any time soon.
> and running an old/distro
> kernel on new HW won't give you useful values unless you provide
> equivalent values in DT, in which case the kernel doesn't need to read
> the registers anyway.
Conversely (and far more likely IMO), running an old/distro devicetree
on a new kernel won't give you usefult values. Bootloaders tend not be
be updated very often (if ever), whereas kernels can (ideally) be
updated without changing userspace.
> The architecture explcitly tells us not to use the values in this way,
> and it's possible to place the values into DT when you know they're
> meaningful.
Well, maybe we can just use these registers for the hundreds of existing
devicetrees that lack values.
--Sean
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