linux-kernel - Re: [PATCH] arm64: cacheinfo: Report cache sets, ways, and line size

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Message-ID: <6d43f466-5786-4957-86c8-8297aa739030@linux.dev>
Date: Mon, 12 May 2025 11:52:02 -0400
From: Sean Anderson <sean.anderson@...ux.dev>
To: Sudeep Holla <sudeep.holla@....com>
Cc: Catalin Marinas <catalin.marinas@....com>,
 linux-arm-kernel@...ts.infradead.org, Radu Rendec <rrendec@...hat.com>,
 Will Deacon <will@...nel.org>,
 Thomas Weißschuh <thomas.weissschuh@...utronix.de>,
 Thomas Gleixner <tglx@...utronix.de>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: cacheinfo: Report cache sets, ways, and line size

On 5/12/25 11:34, Sudeep Holla wrote:
> On Mon, May 12, 2025 at 11:28:36AM -0400, Sean Anderson wrote:
>> On 5/10/25 03:04, Sudeep Holla wrote:
>> > On Fri, May 09, 2025 at 07:37:35PM -0400, Sean Anderson wrote:
>> >> Cache geometry is exposed through the Cache Size ID register. There is
>> >> one register for each cache, and they are selected through the Cache
>> >> Size Selection register. If FEAT_CCIDX is implemented, the layout of
>> >> CCSIDR changes to allow a larger number of sets and ways.
>> >> 
>> > 
>> > Please refer
>> > Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing")
>> > 
>> 
>> | The CCSIDR_EL1.{NumSets,Associativity,LineSize} fields are only for use
>> | in conjunction with set/way cache maintenance and are not guaranteed to
>> | represent the actual microarchitectural features of a design.
>> | 
>> | The architecture explicitly states:
>> | 
>> | | You cannot make any inference about the actual sizes of caches based
>> | | on these parameters.
>> 
>> However, on many cores (A53, A72, and surely others that I haven't
>> checked) these *do* expose the actual microarchitectural features of the
>> design. Maybe a whitelist would be suitable.
>> 
>> | Furthermore, CCSIDR_EL1.{WT,WB,RA,WA} have been removed retrospectively
>> | from ARMv8 and are now considered to be UNKNOWN.
>> | 
>> | Since the kernel doesn't make use of set/way cache maintenance and it is
>> | not possible for userspace to execute these instructions, we have no
>> | need for the CCSIDR information in the kernel.
>> 
>> Actually, these parameters are directly visible (and useful) to
>> userspace in the form of the cache size. Rather than make userspace
>> perform benchmarks, we can expose this information in a standard way.
> 
> Yes that is already present, which is DT or ACPI.
> 
>> There is of course [id]cache-size, but these properties are absent more
>> often than not:
>> 
>> $ git grep arm,cortex- 'arch/arm64/**.dtsi' | wc -l
>> 1248
>> $ git grep d-cache-size 'arch/arm64/**.dtsi' | wc -l
>> 320
>>
> 
> Just to be clear, I am fine with exposing to the userspace, but just
> not reading those registers as stated in the commit message I shared
> earlier.
> 
> Why can't it be done via DT/ACPI ?
> 

Well, do you want to go through 200 SoCs and look up cache info in the
documentation? I think it would be more expedient to look at the TRMs
for two dozen cores and determine if the above registers expose the cache
info correctly.

--Sean