linux-kernel - Re: [PATCH] arm64: cacheinfo: Report cache sets, ways, and line size

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Message-ID: <aCIVec7zl3tIh73h@J2N7QTR9R3>
Date: Mon, 12 May 2025 16:36:25 +0100
From: Mark Rutland <mark.rutland@....com>
To: Sean Anderson <sean.anderson@...ux.dev>
Cc: Sudeep Holla <sudeep.holla@....com>,
	Catalin Marinas <catalin.marinas@....com>,
	linux-arm-kernel@...ts.infradead.org,
	Radu Rendec <rrendec@...hat.com>, Will Deacon <will@...nel.org>,
	Thomas Weißschuh <thomas.weissschuh@...utronix.de>,
	Thomas Gleixner <tglx@...utronix.de>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: cacheinfo: Report cache sets, ways, and line size

On Mon, May 12, 2025 at 11:28:36AM -0400, Sean Anderson wrote:
> On 5/10/25 03:04, Sudeep Holla wrote:
> > On Fri, May 09, 2025 at 07:37:35PM -0400, Sean Anderson wrote:
> >> Cache geometry is exposed through the Cache Size ID register. There is
> >> one register for each cache, and they are selected through the Cache
> >> Size Selection register. If FEAT_CCIDX is implemented, the layout of
> >> CCSIDR changes to allow a larger number of sets and ways.
> >> 
> > 
> > Please refer
> > Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing")
> > 
> 
> | The CCSIDR_EL1.{NumSets,Associativity,LineSize} fields are only for use
> | in conjunction with set/way cache maintenance and are not guaranteed to
> | represent the actual microarchitectural features of a design.
> | 
> | The architecture explicitly states:
> | 
> | | You cannot make any inference about the actual sizes of caches based
> | | on these parameters.
> 
> However, on many cores (A53, A72, and surely others that I haven't
> checked) these *do* expose the actual microarchitectural features of the
> design. Maybe a whitelist would be suitable.

Then we have to maintain a whitelist forever, and running an old/distro
kernel on new HW won't give you useful values unless you provide
equivalent values in DT, in which case the kernel doesn't need to read
the registers anyway.

The architecture explcitly tells us not to use the values in this way,
and it's possible to place the values into DT when you know they're
meaningful.

I do not think we should resurrect the usage of these registers.

Mark.