linux-kernel - [PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

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Message-ID: <20250512-sphere-plenty-8ce4cd772745@spud>
Date: Mon, 12 May 2025 14:48:15 +0100
From: Conor Dooley <conor@...nel.org>
To: linux-renesas-soc@...r.kernel.org
Cc: conor@...nel.org,
	Conor Dooley <conor.dooley@...rochip.com>,
	Ben Zong-You Xie <ben717@...estech.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org
Subject: [PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

From: Conor Dooley <conor.dooley@...rochip.com>

When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.

Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.

Acked-by: Ben Zong-You Xie <ben717@...estech.com>
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index e0ddf8f602c79..a8bcb26f42700 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -143,7 +143,8 @@ plic: interrupt-controller@...00000 {
 	};
 
 	l2cache: cache-controller@...00000 {
-		compatible = "andestech,ax45mp-cache", "cache";
+		compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
+			     "cache";
 		reg = <0x0 0x13400000 0x0 0x100000>;
 		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
 		cache-size = <0x40000>;
-- 
2.45.2