linux-kernel - Re: [PATCH v2 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

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Message-ID: <CAMuHMdUVH+wfdNpNBMdaG3D=z7WcTMmgW2sK_fAgiuJcvLaOig@mail.gmail.com>
Date: Mon, 12 May 2025 15:56:50 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Conor Dooley <conor@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org, 
	Conor Dooley <conor.dooley@...rochip.com>, Ben Zong-You Xie <ben717@...estech.com>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v2 1/2] dt-bindings: cache: add specific RZ/Five
 compatible to ax45mp

On Mon, 12 May 2025 at 15:48, Conor Dooley <conor@...nel.org> wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
>
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
>
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
>
> Acked-by: Ben Zong-You Xie <ben717@...estech.com>
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds