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Message-Id: <174715453733.4022265.13446217787280625298.b4-ty@csie.org>
Date: Wed, 14 May 2025 00:42:17 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Andre Przywara <andre.przywara@....com>
Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] clk: sunxi-ng: d1: Add missing divider for MMC mod
clocks
On Thu, 01 May 2025 13:06:31 +0100, Andre Przywara wrote:
> The D1/R528/T113 SoCs have a hidden divider of 2 in the MMC mod clocks,
> just as other recent SoCs. So far we did not describe that, which led
> to the resulting MMC clock rate to be only half of its intended value.
>
> Use a macro that allows to describe a fixed post-divider, to compensate
> for that divisor.
>
> [...]
Applied to sunxi/clk-fixes-for-6.15 in local tree, thanks!
[1/1] clk: sunxi-ng: d1: Add missing divider for MMC mod clocks
commit: 98e6da673cc6dd46ca9a599802bd2c8f83606710
Best regards,
--
Chen-Yu Tsai <wens@...e.org>
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