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Message-ID: <30570ca0-8da4-4ebc-84d6-0a4badfb7154@intel.com>
Date: Fri, 16 May 2025 06:42:03 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
Borislav Petkov <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>,
x86@...nel.org, "H. Peter Anvin" <hpa@...or.com>
Cc: Jonathan Corbet <corbet@....net>, Andy Lutomirski <luto@...nel.org>,
Peter Zijlstra <peterz@...radead.org>, Ard Biesheuvel <ardb@...nel.org>,
Jan Kiszka <jan.kiszka@...mens.com>, Kieran Bingham <kbingham@...nel.org>,
Michael Roth <michael.roth@....com>,
Rick Edgecombe <rick.p.edgecombe@...el.com>,
Brijesh Singh <brijesh.singh@....com>, Sandipan Das <sandipan.das@....com>,
Juergen Gross <jgross@...e.com>, Tom Lendacky <thomas.lendacky@....com>,
linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
linux-efi@...r.kernel.org, linux-mm@...ck.org
Subject: Re: [PATCHv3 2/4] x86/64/mm: Make SPARSEMEM_VMEMMAP the only memory
model
On 5/16/25 05:33, Kirill A. Shutemov wrote:
> 5-level paging only supports SPARSEMEM_VMEMMAP. CONFIG_X86_5LEVEL is
> being phased out, making 5-level paging support mandatory.
>
> Make CONFIG_SPARSEMEM_VMEMMAP mandatory for x86-64 and eliminate
> any associated conditional statements.
I think we have ourselves a catch-22 here.
SPARSEMEM_VMEMMAP was selected because the other sparsemem modes
couldn't handle a dynamic MAX_PHYS{MEM,ADDR}_BITS introduced by 5-level
paging. Now you're proposing making it static again, but keeping the
SPARSEMEM_VMEMMAP dependency.
If you remove the dynamic MAX_PHYS{MEM,ADDR}_BITS, you should also
remove the dependency on SPARSEMEM_VMEMMAP. No?
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