linux-kernel - [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events

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Message-ID: <174740303900.406.5499797802401271693.tip-bot2@tip-bot2>
Date: Fri, 16 May 2025 13:43:58 -0000
From: "tip-bot2 for Sandipan Das" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Sandipan Das <sandipan.das@....com>, Ingo Molnar <mingo@...nel.org>,
 Peter Zijlstra <peterz@...radead.org>, linux-perf-users@...r.kernel.org,
 x86@...nel.org, linux-kernel@...r.kernel.org
Subject: [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction
 cache events

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     ebe176981c14b5f6472718f9894db35816749120
Gitweb:        https://git.kernel.org/tip/ebe176981c14b5f6472718f9894db35816749120
Author:        Sandipan Das <sandipan.das@....com>
AuthorDate:    Wed, 07 May 2025 17:42:04 +05:30
Committer:     Ingo Molnar <mingo@...nel.org>
CommitterDate: Fri, 16 May 2025 15:32:59 +02:00

perf/x86/amd/core: Fix Family 17h+ instruction cache events

PMCx080 and PMCx081 report incorrect IC accesses and misses respectively
for all Family 17h and later processors. PMCx060 unit mask 0x10 replaces
PMCx081 for counting IC misses but there is no suitable replacement for
counting IC accesses.

Fixes: 0e3b74e26280 ("perf/x86/amd: Update generic hardware cache events for Family 17h")
Signed-off-by: Sandipan Das <sandipan.das@....com>
Signed-off-by: Ingo Molnar <mingo@...nel.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: linux-perf-users@...r.kernel.org
Link: https://lore.kernel.org/r/2f475a1ba4b240111e69644fc2d5bf93b2e39c99.1746618724.git.sandipan.das@amd.com
---
 arch/x86/events/amd/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 30d6ceb..52860b9 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -148,8 +148,8 @@ static __initconst const u64 amd_hw_cache_event_ids_f17h
 },
 [C(L1I)] = {
 	[C(OP_READ)] = {
-		[C(RESULT_ACCESS)] = 0x0080, /* Instruction cache fetches  */
-		[C(RESULT_MISS)]   = 0x0081, /* Instruction cache misses   */
+		[C(RESULT_ACCESS)] = 0,
+		[C(RESULT_MISS)]   = 0x1060, /* L2$ access from IC Miss */
 	},
 	[C(OP_WRITE)] = {
 		[C(RESULT_ACCESS)] = -1,