linux-kernel - [PATCH] perf/x86/amd/core: Fix Family 17h+ instruction cache events

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Message-ID: <2f475a1ba4b240111e69644fc2d5bf93b2e39c99.1746618724.git.sandipan.das@amd.com>
Date: Wed, 7 May 2025 17:42:04 +0530
From: Sandipan Das <sandipan.das@....com>
To: <linux-perf-users@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>, Namhyung Kim
	<namhyung@...nel.org>, Alexander Shishkin
	<alexander.shishkin@...ux.intel.com>, Jiri Olsa <jolsa@...nel.org>, "Ian
 Rogers" <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>, "Kan
 Liang" <kan.liang@...ux.intel.com>, Thomas Gleixner <tglx@...utronix.de>,
	Borislav Petkov <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>,
	<x86@...nel.org>, "H . Peter Anvin" <hpa@...or.com>, Stephane Eranian
	<eranian@...gle.com>, Ravi Bangoria <ravi.bangoria@....com>, Ananth Narayan
	<ananth.narayan@....com>, Sandipan Das <sandipan.das@....com>
Subject: [PATCH] perf/x86/amd/core: Fix Family 17h+ instruction cache events

PMCx080 and PMCx081 report incorrect IC accesses and misses respectively
for all Family 17h and later processors. PMCx060 unit mask 0x10 replaces
PMCx081 for counting IC misses but there is no suitable replacement for
counting IC accesses.

Fixes: 0e3b74e26280 ("perf/x86/amd: Update generic hardware cache events for Family 17h")
Signed-off-by: Sandipan Das <sandipan.das@....com>
---
 arch/x86/events/amd/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 30d6ceb4c8ad..52860b99d70e 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -148,8 +148,8 @@ static __initconst const u64 amd_hw_cache_event_ids_f17h
 },
 [C(L1I)] = {
 	[C(OP_READ)] = {
-		[C(RESULT_ACCESS)] = 0x0080, /* Instruction cache fetches  */
-		[C(RESULT_MISS)]   = 0x0081, /* Instruction cache misses   */
+		[C(RESULT_ACCESS)] = 0,
+		[C(RESULT_MISS)]   = 0x1060, /* L2$ access from IC Miss */
 	},
 	[C(OP_WRITE)] = {
 		[C(RESULT_ACCESS)] = -1,
-- 
2.43.0