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Message-Id: <20250516-dtb-check-mt8188-v2-2-fb60bef1b8e1@collabora.com>
Date: Fri, 16 May 2025 16:12:14 +0200
From: Julien Massot <julien.massot@...labora.com>
To: kernel@...labora.com, Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Garmin Chang <garmin.chang@...iatek.com>,
Friday Yang <friday.yang@...iatek.com>
Cc: Conor Dooley <conor.dooley@...rochip.com>, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
Julien Massot <julien.massot@...labora.com>
Subject: [PATCH v2 2/2] arm64: dts: mediatek: mt8188: Add missing
#reset-cells property
The binding now require the '#reset-cells' property but the
devicetree has not been updated which trigger dtb-check errors.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Signed-off-by: Julien Massot <julien.massot@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt8188.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 296090fbaf4953db8075f72073509b731dc41e51..dec6ce3e94e92c8e1e2c3680cb3584394d9058bd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -2647,36 +2647,42 @@ imgsys1_dip_top: clock-controller@...10000 {
compatible = "mediatek,mt8188-imgsys1-dip-top";
reg = <0 0x15110000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
imgsys1_dip_nr: clock-controller@...30000 {
compatible = "mediatek,mt8188-imgsys1-dip-nr";
reg = <0 0x15130000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
imgsys_wpe1: clock-controller@...20000 {
compatible = "mediatek,mt8188-imgsys-wpe1";
reg = <0 0x15220000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
ipesys: clock-controller@...30000 {
compatible = "mediatek,mt8188-ipesys";
reg = <0 0x15330000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
imgsys_wpe2: clock-controller@...20000 {
compatible = "mediatek,mt8188-imgsys-wpe2";
reg = <0 0x15520000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
imgsys_wpe3: clock-controller@...20000 {
compatible = "mediatek,mt8188-imgsys-wpe3";
reg = <0 0x15620000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
camsys: clock-controller@...00000 {
@@ -2689,24 +2695,28 @@ camsys_rawa: clock-controller@...4f000 {
compatible = "mediatek,mt8188-camsys-rawa";
reg = <0 0x1604f000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
camsys_yuva: clock-controller@...6f000 {
compatible = "mediatek,mt8188-camsys-yuva";
reg = <0 0x1606f000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
camsys_rawb: clock-controller@...8f000 {
compatible = "mediatek,mt8188-camsys-rawb";
reg = <0 0x1608f000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
camsys_yuvb: clock-controller@...af000 {
compatible = "mediatek,mt8188-camsys-yuvb";
reg = <0 0x160af000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
ccusys: clock-controller@...00000 {
--
2.49.0
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