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Message-ID: <CAJZ5v0hGVYyHX7ZQPQ5XNrHBBy9jfA+WMLu7XaoXAqr3s4dOfg@mail.gmail.com>
Date: Fri, 16 May 2025 16:12:46 +0200
From: "Rafael J. Wysocki" <rafael@...nel.org>
To: Sunil V L <sunilvl@...tanamicro.com>
Cc: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-acpi@...r.kernel.org, iommu@...ts.linux.dev,
acpica-devel@...ts.linux.dev, Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>, "Rafael J . Wysocki" <rafael@...nel.org>, Len Brown <lenb@...nel.org>,
Tomasz Jeznach <tjeznach@...osinc.com>, Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>, Atish Kumar Patra <atishp@...osinc.com>,
Anup Patel <apatel@...tanamicro.com>, Andrew Jones <ajones@...tanamicro.com>
Subject: Re: [PATCH 1/4] ACPICA: actbl2: Add definitions for RIMT
On Wed, May 14, 2025 at 7:57 AM Sunil V L <sunilvl@...tanamicro.com> wrote:
>
> ACPICA commit 73c32bc89cad64ab19c1231a202361e917e6823c
>
> RISC-V IO Mapping Table (RIMT) is a new static table defined for RISC-V
> to communicate IOMMU information to the OS. The specification for RIMT
> is available at [1]. Add structure definitions for RIMT.
>
> [1] - https://github.com/riscv-non-isa/riscv-acpi-rimt
>
> Link: https://github.com/acpica/acpica/commit/73c32bc8
> Signed-off-by: Sunil V L <sunilvl@...tanamicro.com>
An analogous patch is present in linux-next already as
ced63370237a ACPICA: actbl2: Add definitions for RIMT
No need to send this again.
> ---
> include/acpi/actbl2.h | 83 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
>
> diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
> index 2e917a8f8bca..99ea8bfe47de 100644
> --- a/include/acpi/actbl2.h
> +++ b/include/acpi/actbl2.h
> @@ -50,6 +50,7 @@
> #define ACPI_SIG_RAS2 "RAS2" /* RAS2 Feature table */
> #define ACPI_SIG_RGRT "RGRT" /* Regulatory Graphics Resource Table */
> #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
> +#define ACPI_SIG_RIMT "RIMT" /* RISC-V IO Mapping Table */
> #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */
> #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */
> #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */
> @@ -3002,6 +3003,88 @@ struct acpi_rhct_hart_info {
> u32 uid; /* ACPI processor UID */
> };
>
> +/*******************************************************************************
> + *
> + * RIMT - RISC-V IO Remapping Table
> + *
> + * https://github.com/riscv-non-isa/riscv-acpi-rimt
> + *
> + ******************************************************************************/
> +
> +struct acpi_table_rimt {
> + struct acpi_table_header header; /* Common ACPI table header */
> + u32 num_nodes; /* Number of RIMT Nodes */
> + u32 node_offset; /* Offset to RIMT Node Array */
> + u32 reserved;
> +};
> +
> +struct acpi_rimt_node {
> + u8 type;
> + u8 revision;
> + u16 length;
> + u16 reserved;
> + u16 id;
> + char node_data[];
> +};
> +
> +enum acpi_rimt_node_type {
> + ACPI_RIMT_NODE_TYPE_IOMMU = 0x0,
> + ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX = 0x1,
> + ACPI_RIMT_NODE_TYPE_PLAT_DEVICE = 0x2,
> +};
> +
> +struct acpi_rimt_iommu {
> + u8 hardware_id[8]; /* Hardware ID */
> + u64 base_address; /* Base Address */
> + u32 flags; /* Flags */
> + u32 proximity_domain; /* Proximity Domain */
> + u16 pcie_segment_number; /* PCIe Segment number */
> + u16 pcie_bdf; /* PCIe B/D/F */
> + u16 num_interrupt_wires; /* Number of interrupt wires */
> + u16 interrupt_wire_offset; /* Interrupt wire array offset */
> + u64 interrupt_wire[]; /* Interrupt wire array */
> +};
> +
> +/* IOMMU Node Flags */
> +#define ACPI_RIMT_IOMMU_FLAGS_PCIE (1)
> +#define ACPI_RIMT_IOMMU_FLAGS_PXM_VALID (1 << 1)
> +
> +/* Interrupt Wire Structure */
> +struct acpi_rimt_iommu_wire_gsi {
> + u32 irq_num; /* Interrupt Number */
> + u32 flags; /* Flags */
> +};
> +
> +/* Interrupt Wire Flags */
> +#define ACPI_RIMT_GSI_LEVEL_TRIGGERRED (1)
> +#define ACPI_RIMT_GSI_ACTIVE_HIGH (1 << 1)
> +
> +struct acpi_rimt_id_mapping {
> + u32 source_id_base; /* Source ID Base */
> + u32 num_ids; /* Number of IDs */
> + u32 dest_id_base; /* Destination Device ID Base */
> + u32 dest_offset; /* Destination IOMMU Offset */
> + u32 flags; /* Flags */
> +};
> +
> +struct acpi_rimt_pcie_rc {
> + u32 flags; /* Flags */
> + u16 reserved; /* Reserved */
> + u16 pcie_segment_number; /* PCIe Segment number */
> + u16 id_mapping_offset; /* ID mapping array offset */
> + u16 num_id_mappings; /* Number of ID mappings */
> +};
> +
> +/* PCIe Root Complex Node Flags */
> +#define ACPI_RIMT_PCIE_ATS_SUPPORTED (1)
> +#define ACPI_RIMT_PCIE_PRI_SUPPORTED (1 << 1)
> +
> +struct acpi_rimt_platform_device {
> + u16 id_mapping_offset; /* ID Mapping array offset */
> + u16 num_id_mappings; /* Number of ID mappings */
> + char device_name[]; /* Device Object Name */
> +};
> +
> /*******************************************************************************
> *
> * SBST - Smart Battery Specification Table
> --
> 2.43.0
>
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