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Message-ID: <20250518220812.1480696-1-john.madieu.xa@bp.renesas.com>
Date: Mon, 19 May 2025 00:08:12 +0200
From: John Madieu <john.madieu.xa@...renesas.com>
To: geert+renesas@...der.be,
magnus.damm@...il.com,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org
Cc: biju.das.jz@...renesas.com,
linux-renesas-soc@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
John Madieu <john.madieu.xa@...renesas.com>
Subject: [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2 clock frequency
Lower the I2C2 bus clock frequency on the RZ/G3E SMARC SoM from 1MHz to 400KHz
to improve compatibility with a wider range of I2C peripherals. The previous
1MHz setting was too aggressive for some devices on the bus, which experienced
timing issues at such a frequency.
Fixes: f7a98e256ee3 ("arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrol")
Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>
---
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index 43d79158d81a..ecea29a76b14 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -85,7 +85,7 @@ &gpu {
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
- clock-frequency = <1000000>;
+ clock-frequency = <400000>;
status = "okay";
raa215300: pmic@12 {
--
2.43.0
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