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Message-ID: <aCrN4TCplWsxNPVE@shikoro>
Date: Mon, 19 May 2025 08:21:21 +0200
From: Wolfram Sang <wsa+renesas@...g-engineering.com>
To: John Madieu <john.madieu.xa@...renesas.com>
Cc: geert+renesas@...der.be, magnus.damm@...il.com, robh@...nel.org,
	krzk+dt@...nel.org, conor+dt@...nel.org, biju.das.jz@...renesas.com,
	linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2
 clock frequency

On Mon, May 19, 2025 at 12:08:12AM +0200, John Madieu wrote:
> Lower the I2C2 bus clock frequency on the RZ/G3E SMARC SoM from 1MHz to 400KHz
> to improve compatibility with a wider range of I2C peripherals. The previous
> 1MHz setting was too aggressive for some devices on the bus, which experienced
> timing issues at such a frequency.
> 
> Fixes: f7a98e256ee3 ("arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrol")
> Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@...g-engineering.com>


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