linux-kernel - [PATCH 3/3] arm64: dts: renesas: Add pinctrl for renesas RZ/T2H SoC

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Message-ID: <20250519215734.577053-4-thierry.bultel.yh@bp.renesas.com>
Date: Mon, 19 May 2025 23:57:33 +0200
From: Thierry Bultel <thierry.bultel.yh@...renesas.com>
To: thierry.bultel@...atsea.fr
Cc: linux-renesas-soc@...r.kernel.org,
	geert@...ux-m68k.org,
	paul.barker.ct@...renesas.com,
	Thierry Bultel <thierry.bultel.yh@...renesas.com>,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH 3/3] arm64: dts: renesas: Add pinctrl for renesas RZ/T2H SoC

Add pinctrl node for r9a09g077

Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 48b889da9095..5648071660ab 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -101,6 +101,15 @@ cpg: clock-controller@...80000 {
 			#power-domain-cells = <0>;
 		};
 
+		pinctrl: pinctrl@...c0000 {
+			compatible = "renesas,pfc-r9a09g077";
+			reg = <0 0x802c0000 0 0x2000>,
+			      <0 0x812c0000 0 0x2000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 287>;
+		};
+
 		gic: interrupt-controller@...00000 {
 			compatible = "arm,gic-v3";
 			reg = <0x0 0x83000000 0 0x40000>,
-- 
2.43.0