linux-kernel - Re: [PATCH v3 0/2] riscv: sophgo Add PCIe support to Sophgo SG2044 SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <77tip2z2mmuucsi4ackwubfdbyzgg2soaosmvbyrfl3iwrmmp3@icjunp4bsske>
Date: Mon, 19 May 2025 19:43:17 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>, 
	Krzysztof Wilczyński <kw@...ux.com>, Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, 
	Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Chen Wang <unicorn_wang@...look.com>, Inochi Amaoto <inochiama@...il.com>, 
	Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, 
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>, 
	Niklas Cassel <cassel@...nel.org>, Johan Hovold <johan+linaro@...nel.org>, 
	Shradha Todi <shradha.t@...sung.com>, Thippeswamy Havalige <thippeswamy.havalige@....com>, 
	Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org, 
	sophgo@...ts.linux.dev, linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, 
	Yixun Lan <dlan@...too.org>, Longbin Li <looong.bin@...il.com>
Subject: Re: [PATCH v3 0/2] riscv: sophgo Add PCIe support to Sophgo SG2044
 SoC

On Sun, May 04, 2025 at 08:44:17AM +0800, Inochi Amaoto wrote:
> Sophgo's SG2044 SoC uses Synopsys Designware PCIe core
> to implement RC mode.
> 
> For legacy interrupt, the PCIe controller on SG2044 implement
> its own legacy interrupt controller. For MSI/MSI-X, it use an
> external interrupt controller to handle.
> 
> The external MSI interrupt controller patch can be found on [1].
> As SG2044 needs a mirror change to support the way to send MSI
> message and different irq number.
> 
> [1] https://lore.kernel.org/all/20250413224922.69719-1-inochiama@gmail.com
> 
> Changed from v2:
> - https://lore.kernel.org/all/20250304071239.352486-1-inochiama@gmail.com
> 1. patch 1: remove "|+" for description
> 2. patch 1: apply Rob's tag
> 3. patch 2: remove empty irq_eoi and use handle_level_irq as the right
> 	    irq handle function.
> 
> Changed from v1:
> - https://lore.kernel.org/all/20250221013758.370936-1-inochiama@gmail.com
> 1. patch 1: remove dma-coherent property
> 2. patch 2: remove unused reset
> 3. patch 2: fix Kconfig menu title and reorder the entry
> 4. patch 2: use FIELD_GET/FIELD_PREP to simplify the code.
> 5. patch 2: rename the irq handle function to match the irq_chip name
> 
> Inochi Amaoto (2):
>   dt-bindings: pci: Add Sophgo SG2044 PCIe host
>   PCI: sophgo-dwc: Add Sophgo SG2044 PCIe driver
> 
>  .../bindings/pci/sophgo,sg2044-pcie.yaml      | 122 +++++++++
>  drivers/pci/controller/dwc/Kconfig            |  10 +
>  drivers/pci/controller/dwc/Makefile           |   1 +
>  drivers/pci/controller/dwc/pcie-dw-sophgo.c   | 258 ++++++++++++++++++
>  4 files changed, 391 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
>  create mode 100644 drivers/pci/controller/dwc/pcie-dw-sophgo.c
> 
> --
> 2.49.0
> 

It is a long time for this series without any comment, I wonder
that this patch could be picked for 6.16?

Regard,
Inochi