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Message-ID: <174979096373.22387.8666752122012744282.b4-ty@kernel.org>
Date: Fri, 13 Jun 2025 10:32:54 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>,
Rob Herring <robh@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Chen Wang <unicorn_wang@...look.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>,
Niklas Cassel <cassel@...nel.org>,
Johan Hovold <johan+linaro@...nel.org>,
Shradha Todi <shradha.t@...sung.com>,
Thippeswamy Havalige <thippeswamy.havalige@....com>,
Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>,
Krzysztof WilczyĆski <kwilczynski@...nel.org>,
Manivannan Sadhasivam <mani@...nel.org>,
Inochi Amaoto <inochiama@...il.com>
Cc: linux-pci@...r.kernel.org,
devicetree@...r.kernel.org,
sophgo@...ts.linux.dev,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Yixun Lan <dlan@...too.org>,
Longbin Li <looong.bin@...il.com>
Subject: Re: [PATCH v3 0/2] riscv: sophgo Add PCIe support to Sophgo SG2044 SoC
On Sun, 04 May 2025 08:44:17 +0800, Inochi Amaoto wrote:
> Sophgo's SG2044 SoC uses Synopsys Designware PCIe core
> to implement RC mode.
>
> For legacy interrupt, the PCIe controller on SG2044 implement
> its own legacy interrupt controller. For MSI/MSI-X, it use an
> external interrupt controller to handle.
>
> [...]
Applied, thanks!
[1/2] dt-bindings: pci: Add Sophgo SG2044 PCIe host
commit: a202f09e3e30622fdcae7d740dbf87fb0f032dd5
[2/2] PCI: sophgo-dwc: Add Sophgo SG2044 PCIe driver
commit: 74ab255bab3082fa6bd2a925a986526e093d615b
Best regards,
--
Manivannan Sadhasivam <mani@...nel.org>
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