| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <1513350b-7de3-405a-b6c5-fcaf9efebf3b@linux.intel.com>
Date: Wed, 21 May 2025 16:12:15 -0400
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: Namhyung Kim <namhyung@...nel.org>, Mingwei Zhang <mizhang@...gle.com>
Cc: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Sean Christopherson <seanjc@...gle.com>, Paolo Bonzini
<pbonzini@...hat.com>, Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>, Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>, Liang@...gle.com,
"H. Peter Anvin" <hpa@...or.com>, linux-perf-users@...r.kernel.org,
linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
linux-kselftest@...r.kernel.org, Yongwei Ma <yongwei.ma@...el.com>,
Xiong Zhang <xiong.y.zhang@...ux.intel.com>,
Dapeng Mi <dapeng1.mi@...ux.intel.com>, Jim Mattson <jmattson@...gle.com>,
Sandipan Das <sandipan.das@....com>, Zide Chen <zide.chen@...el.com>,
Eranian Stephane <eranian@...gle.com>, Shukla Manali
<Manali.Shukla@....com>, Nikunj Dadhania <nikunj.dadhania@....com>
Subject: Re: [PATCH v4 05/38] perf: Add generic exclude_guest support
On 2025-05-21 3:55 p.m., Namhyung Kim wrote:
> On Mon, Mar 24, 2025 at 05:30:45PM +0000, Mingwei Zhang wrote:
>> From: Kan Liang <kan.liang@...ux.intel.com>
>>
>> Only KVM knows the exact time when a guest is entering/exiting. Expose
>> two interfaces to KVM to switch the ownership of the PMU resources.
>>
>> All the pinned events must be scheduled in first. Extend the
>> perf_event_sched_in() helper to support extra flag, e.g., EVENT_GUEST.
>>
>> Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
>> Signed-off-by: Mingwei Zhang <mizhang@...gle.com>
>> ---
>> include/linux/perf_event.h | 4 ++
>> kernel/events/core.c | 80 ++++++++++++++++++++++++++++++++++----
>> 2 files changed, 77 insertions(+), 7 deletions(-)
>>
>> diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
>> index 7bda1e20be12..37187ee8e226 100644
>> --- a/include/linux/perf_event.h
>> +++ b/include/linux/perf_event.h
>> @@ -1822,6 +1822,8 @@ extern int perf_event_period(struct perf_event *event, u64 value);
>> extern u64 perf_event_pause(struct perf_event *event, bool reset);
>> int perf_get_mediated_pmu(void);
>> void perf_put_mediated_pmu(void);
>> +void perf_guest_enter(void);
>> +void perf_guest_exit(void);
>> #else /* !CONFIG_PERF_EVENTS: */
>> static inline void *
>> perf_aux_output_begin(struct perf_output_handle *handle,
>> @@ -1919,6 +1921,8 @@ static inline int perf_get_mediated_pmu(void)
>> }
>>
>> static inline void perf_put_mediated_pmu(void) { }
>> +static inline void perf_guest_enter(void) { }
>> +static inline void perf_guest_exit(void) { }
>> #endif
>>
>> #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
>> diff --git a/kernel/events/core.c b/kernel/events/core.c
>> index 7a2115b2c5c1..d05487d465c9 100644
>> --- a/kernel/events/core.c
>> +++ b/kernel/events/core.c
>> @@ -2827,14 +2827,15 @@ static void task_ctx_sched_out(struct perf_event_context *ctx,
>>
>> static void perf_event_sched_in(struct perf_cpu_context *cpuctx,
>> struct perf_event_context *ctx,
>> - struct pmu *pmu)
>> + struct pmu *pmu,
>> + enum event_type_t event_type)
>> {
>> - ctx_sched_in(&cpuctx->ctx, pmu, EVENT_PINNED);
>> + ctx_sched_in(&cpuctx->ctx, pmu, EVENT_PINNED | event_type);
>> if (ctx)
>> - ctx_sched_in(ctx, pmu, EVENT_PINNED);
>> - ctx_sched_in(&cpuctx->ctx, pmu, EVENT_FLEXIBLE);
>> + ctx_sched_in(ctx, pmu, EVENT_PINNED | event_type);
>> + ctx_sched_in(&cpuctx->ctx, pmu, EVENT_FLEXIBLE | event_type);
>> if (ctx)
>> - ctx_sched_in(ctx, pmu, EVENT_FLEXIBLE);
>> + ctx_sched_in(ctx, pmu, EVENT_FLEXIBLE | event_type);
>> }
>>
>> /*
>> @@ -2890,7 +2891,7 @@ static void ctx_resched(struct perf_cpu_context *cpuctx,
>> else if (event_type & EVENT_PINNED)
>> ctx_sched_out(&cpuctx->ctx, pmu, EVENT_FLEXIBLE);
>>
>> - perf_event_sched_in(cpuctx, task_ctx, pmu);
>> + perf_event_sched_in(cpuctx, task_ctx, pmu, 0);
>>
>> for_each_epc(epc, &cpuctx->ctx, pmu, 0)
>> perf_pmu_enable(epc->pmu);
>> @@ -4188,7 +4189,7 @@ static void perf_event_context_sched_in(struct task_struct *task)
>> ctx_sched_out(&cpuctx->ctx, NULL, EVENT_FLEXIBLE);
>> }
>>
>> - perf_event_sched_in(cpuctx, ctx, NULL);
>> + perf_event_sched_in(cpuctx, ctx, NULL, 0);
>>
>> perf_ctx_sched_task_cb(cpuctx->task_ctx, true);
>>
>> @@ -6040,6 +6041,71 @@ void perf_put_mediated_pmu(void)
>> }
>> EXPORT_SYMBOL_GPL(perf_put_mediated_pmu);
>>
>> +static inline void perf_host_exit(struct perf_cpu_context *cpuctx)
>> +{
>> + perf_ctx_disable(&cpuctx->ctx, EVENT_GUEST);
>> + ctx_sched_out(&cpuctx->ctx, NULL, EVENT_GUEST);
>> + perf_ctx_enable(&cpuctx->ctx, EVENT_GUEST);
>> + if (cpuctx->task_ctx) {
>> + perf_ctx_disable(cpuctx->task_ctx, EVENT_GUEST);
>> + task_ctx_sched_out(cpuctx->task_ctx, NULL, EVENT_GUEST);
>> + perf_ctx_enable(cpuctx->task_ctx, EVENT_GUEST);
>> + }
>> +}
>
> Cpu context and task context may have events in the same PMU.
> How about this?
>
> perf_ctx_disable(&cpuctx->ctx, EVENT_GUEST);
> if (cpuctx->task_ctx)
> perf_ctx_disable(cpuctx->task_ctx, EVENT_GUEST);
>
> ctx_sched_out(&cpuctx->ctx, NULL, EVENT_GUEST);
> if (cpuctx->task_ctx)
> task_ctx_sched_out(cpuctx->task_ctx, NULL, EVENT_GUEST);
>
> if (cpuctx->task_ctx)
> perf_ctx_enable(cpuctx->task_ctx, EVENT_GUEST);
> perf_ctx_enable(&cpuctx->ctx, EVENT_GUEST);
>
Yes, this is what has to be fixed in V4.
No matter for load context or put context, I think the below steps have
to be followed.
- Disable both cpuctx->ctx and cpuctx->task_ctx
- schedule in/out host counters and load/put guest countext
- Enable both cpuctx->ctx and cpuctx->task_ctx
A similar proposed can be found at
https://lore.kernel.org/lkml/4aaf67ab-aa5c-41e6-bced-3cb000172c52@linux.intel.com/
Thanks,
Kan
Powered by blists - more mailing lists