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Message-ID: <87jz69raly.ffs@tglx>
Date: Wed, 21 May 2025 22:07:37 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Borislav Petkov <bp@...en8.de>
Cc: Ingo Molnar <mingo@...nel.org>, "Ahmed S. Darwish"
<darwi@...utronix.de>, Ard Biesheuvel <ardb+git@...gle.com>,
linux-kernel@...r.kernel.org, x86@...nel.org, Ard Biesheuvel
<ardb@...nel.org>, Linus Torvalds <torvalds@...ux-foundation.org>, Brian
Gerst <brgerst@...il.com>, "Kirill A. Shutemov" <kirill@...temov.name>
Subject: Re: [PATCH v4 1/6] x86/cpu: Use a new feature flag for 5 level paging
On Wed, May 21 2025 at 21:48, Borislav Petkov wrote:
> On Wed, May 21, 2025 at 09:41:00PM +0200, Thomas Gleixner wrote:
>> In the long run we really want to disable user space CPUID and emulate
>> it when the hardware supports CPUID faulting, which should be made an
>> architectural feature IMO.
>
> Both vendors do support it. I probably should do the AMD side. It is about
> time...
Both vendors support it, but it's not an architectural feature and it
really should be one.
That ensures it can't go away just because some hardware dude thinks
again that the three extra gates are overkill as all of this can be
handled in software ....
Thanks,
tglx
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