linux-kernel - Re: [PATCH v4 08/18] clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe

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Message-ID: <264c7738-3fc3-4712-8880-cb150c8c44f1@quicinc.com>
Date: Wed, 21 May 2025 15:13:50 +0530
From: Jagadeesh Kona <quic_jkona@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Bjorn Andersson
	<andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        "Stephen
 Boyd" <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Konrad Dybcio
	<konradybcio@...nel.org>,
        Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>,
        Dmitry Baryshkov <lumag@...nel.org>
CC: Ajit Pandey <quic_ajipan@...cinc.com>,
        Imran Shaik
	<quic_imrashai@...cinc.com>,
        Taniya Das <quic_tdas@...cinc.com>,
        "Satya Priya
 Kakitapalli" <quic_skakitap@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski@...aro.org>,
        Bryan O'Donoghue
	<bryan.odonoghue@...aro.org>,
        Dmitry Baryshkov
	<dmitry.baryshkov@....qualcomm.com>
Subject: Re: [PATCH v4 08/18] clk: qcom: videocc-sm8550: Move PLL & clk
 configuration to really probe



On 5/15/2025 9:08 PM, Konrad Dybcio wrote:
> On 5/14/25 9:08 PM, Jagadeesh Kona wrote:
>> Video PLLs on SM8550/SM8650 require both MMCX and MXC rails to be kept ON
>> to configure the PLLs properly. Hence move runtime power management, PLL
>> configuration and enable critical clocks to qcom_cc_really_probe() which
>> ensures all required power domains are in enabled state before configuring
>> the PLLs or enabling the clocks.
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@...cinc.com>
>> ---
> 
> [...]
> 
>> -
>> -	pm_runtime_put(&pdev->dev);
>> +		/* Sleep clock offset changed to 0x8150 on SM8650 */
>> +		video_cc_sm8550_critical_cbcrs[2] = 0x8150;
>> +	}
> 
> Because we tend to sort these by address, this index will likely break
> the next time someone touches this
> 
> please introduce a separate array for 8650 instead
> 

Sure, will introduce separate array for SM8650 in next series.

Thanks,
Jagadeesh

> Konrad