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Message-ID: <CAMpQs4JRy+Q2D5B9cOLyuD=8EcWNqqyhJcm+X5wiqTgjy5cikA@mail.gmail.com>
Date: Fri, 23 May 2025 20:30:57 +0800
From: Binbin Zhou <zhoubb.aaron@...il.com>
To: Yao Zi <ziyao@...root.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Huacai Chen <chenhuacai@...nel.org>, WANG Xuerui <kernel@...0n.name>,
Yinbo Zhu <zhuyinbo@...ngson.cn>, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
loongarch@...ts.linux.dev, Mingcong Bai <jeffbai@...c.io>,
Kexy Biscuit <kexybiscuit@...c.io>
Subject: Re: [PATCH 1/8] dt-bindings: clock: Document Loongson 2K0300 clock controller
On Fri, May 23, 2025 at 6:46 PM Yao Zi <ziyao@...root.org> wrote:
>
> Document the clock controller shipped in Loongson 2K0300 SoC, which
> generates various clock signals for SoC peripherals.
>
> Signed-off-by: Yao Zi <ziyao@...root.org>
> ---
> .../bindings/clock/loongson,ls2k0300-clk.yaml | 52 ++++++++++++++++++
> .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++
> 2 files changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/loongson,ls2k0300-clk.yaml
I don't think a new binding file for 2K0300 is needed. Adding
compatible entries to loongson,ls2k-clk.yaml would be more appropriate
as they are almost all similar.
> create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h
>
> diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k0300-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k0300-clk.yaml
> new file mode 100644
> index 000000000000..d96b9d7cb7c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k0300-clk.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/loongson,ls2k0300-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson-2K0300 SoC Clock Controller
> +
> +maintainers:
> + - Yao Zi <ziyao@...root.org>
> +
> +description: |
> + The Loongson 2K0300 clock controller generates various clocks for SoC
> + peripherals. See include/dt-bindings/clock/loongson,ls2k0300-clk.h for
> + valid clock IDs.
> +
> +properties:
> + compatible:
> + const: loongson,ls2k0300-clk
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: External 120MHz reference clock
> +
> + clock-names:
> + items:
> + - const: ref_120m
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clk: clock-controller@...00400 {
> + compatible = "loongson,ls2k0300-clk";
> + reg = <0x16000400 0x100>;
> + clocks = <&ref_120m>;
> + clock-names = "ref_120m";
> + #clock-cells = <1>;
> + };
> diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt-bindings/clock/loongson,ls2k0300-clk.h
> new file mode 100644
> index 000000000000..5e8f7b2f33f2
> --- /dev/null
> +++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (C) 2025 Yao Zi <ziyao@...root.org>
> + */
> +#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> +#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> +
> +/* Derivied from REFCLK */
> +#define LS2K0300_CLK_STABLE 0
> +#define LS2K0300_PLL_NODE 1
> +#define LS2K0300_PLL_DDR 2
> +#define LS2K0300_PLL_PIX 3
> +#define LS2K0300_CLK_THSENS 4
> +
> +/* Derived from PLL_NODE */
> +#define LS2K0300_CLK_NODE_DIV 5
> +#define LS2K0300_CLK_NODE_PLL_GATE 6
> +#define LS2K0300_CLK_NODE_SCALE 7
> +#define LS2K0300_CLK_NODE_GATE 8
> +#define LS2K0300_CLK_GMAC_DIV 9
> +#define LS2K0300_CLK_GMAC_GATE 10
> +#define LS2K0300_CLK_I2S_DIV 11
> +#define LS2K0300_CLK_I2S_SCALE 12
> +#define LS2K0300_CLK_I2S_GATE 13
> +
> +/* Derived from PLL_DDR */
> +#define LS2K0300_CLK_DDR_DIV 14
> +#define LS2K0300_CLK_DDR_GATE 15
> +#define LS2K0300_CLK_NET_DIV 16
> +#define LS2K0300_CLK_NET_GATE 17
> +#define LS2K0300_CLK_DEV_DIV 18
> +#define LS2K0300_CLK_DEV_GATE 19
> +
> +/* Derived from PLL_PIX */
> +#define LS2K0300_CLK_PIX_DIV 20
> +#define LS2K0300_CLK_PIX_PLL_GATE 21
> +#define LS2K0300_CLK_PIX_SCALE 22
> +#define LS2K0300_CLK_PIX_GATE 23
> +#define LS2K0300_CLK_GMACBP_DIV 24
> +#define LS2K0300_CLK_GMACBP_GATE 25
> +
> +/* Derived from CLK_DEV */
> +#define LS2K0300_CLK_USB_SCALE 26
> +#define LS2K0300_CLK_USB_GATE 27
> +#define LS2K0300_CLK_APB_SCALE 28
> +#define LS2K0300_CLK_APB_GATE 29
> +#define LS2K0300_CLK_BOOT_SCALE 30
> +#define LS2K0300_CLK_BOOT_GATE 31
> +#define LS2K0300_CLK_SDIO_SCALE 32
> +#define LS2K0300_CLK_SDIO_GATE 33
> +
> +#define LS2K0300_CLK_GMAC_IN 34
> +
> +#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> --
> 2.49.0
>
>
--
Thanks.
Binbin
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