linux-kernel - Re: [PATCH 2/5] clk: qcom: gcc-ipq5018: fix GE PHY reset

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Message-ID:
 <DS7PR19MB8883BE13166F7CD5DCA777DB9D64A@DS7PR19MB8883.namprd19.prod.outlook.com>
Date: Tue, 27 May 2025 15:14:23 +0400
From: George Moussalem <george.moussalem@...look.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
 Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
 Russell King <linux@...linux.org.uk>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Florian Fainelli <f.fainelli@...il.com>,
 Philipp Zabel <p.zabel@...gutronix.de>,
 Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
 linux-clk@...r.kernel.org
Subject: Re: [PATCH 2/5] clk: qcom: gcc-ipq5018: fix GE PHY reset

Hi Konrad,

On 5/27/25 15:00, Konrad Dybcio wrote:
> On 5/25/25 7:56 PM, George Moussalem via B4 Relay wrote:
>> From: George Moussalem <george.moussalem@...look.com>
>>
>> The MISC reset is supposed to trigger a resets across the MDC, DSP, and
>> RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask
>> of the reset definition accordingly in the GCC as per the downstream
>> driver.
>>
>> Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932
>>
>> Signed-off-by: George Moussalem <george.moussalem@...look.com>
>> ---
>>   drivers/clk/qcom/gcc-ipq5018.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
>> index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..02d6f08f389f24eccc961b9a4271288c6b635bbc 100644
>> --- a/drivers/clk/qcom/gcc-ipq5018.c
>> +++ b/drivers/clk/qcom/gcc-ipq5018.c
>> @@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = {
>>   	[GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
>>   	[GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
>>   	[GCC_WCSSAON_RESET] = { 0x59010, 0},
>> -	[GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
>> +	[GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = 0xf },
> 
> The computer tells me there aren't any bits beyond this mask..
> 
> Does this actually fix anything?

The mask is documented in the referenced downstream driver and allows 
for consolidating:

resets = <&gcc GCC_GEPHY_MDC_SW_ARES>,
	 <&gcc GCC_GEPHY_DSP_HW_ARES>,
	 <&gcc GCC_GEPHY_RX_ARES>,
	 <&gcc GCC_GEPHY_TX_ARES>;
to:

resets = <&gcc GCC_MISC_ARES>;

to conform to this bindings restriction in ethernet-phy.yaml

   resets:
     maxItems: 1

Effectively, there's no functional change. So we can also list all the 
resets in the device tree, whatever is preferred.

> 
> Konrad

Thanks,
George