linux-kernel - Re: [v10 PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property

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Message-ID: <4dc85254-215c-4826-a157-b755b738dd5a@kernel.org>
Date: Wed, 28 May 2025 07:54:16 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Vijay Balakrishna <vijayb@...ux.microsoft.com>,
 Borislav Petkov <bp@...en8.de>, Tony Luck <tony.luck@...el.com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>
Cc: James Morse <james.morse@....com>,
 Mauro Carvalho Chehab <mchehab@...nel.org>, Robert Richter
 <rric@...nel.org>, linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org,
 Tyler Hicks <code@...icks.com>, Marc Zyngier <maz@...nel.org>,
 Sascha Hauer <s.hauer@...gutronix.de>,
 Lorenzo Pieralisi <lpieralisi@...nel.org>, devicetree@...r.kernel.org
Subject: Re: [v10 PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property

On 28/05/2025 01:16, Vijay Balakrishna wrote:
> From: Sascha Hauer <s.hauer@...gutronix.de>
> 
> Some ARM Cortex CPUs including A72 have Error Detection And
> Correction (EDAC) support on their L1 and L2 caches. This is implemented
> in implementation defined registers, so usage of this functionality is
> not safe in virtualized environments or when EL3 already uses these
> registers. This patch adds a edac-enabled flag which can be explicitly
> set when EDAC can be used.
> 
> Signed-off-by: Sascha Hauer <s.hauer@...gutronix.de>
> [vijayb: Added A72 to the commit message]
> Signed-off-by: Vijay Balakrishna <vijayb@...ux.microsoft.com>
> ---
>  .../devicetree/bindings/arm/cpus.yaml         | 51 +++++++++++++------
>  1 file changed, 35 insertions(+), 16 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index 2e666b2a4dcd..8f42c4fec59b 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -331,6 +331,13 @@ properties:
>        corresponding to the index of an SCMI performance domain provider, must be
>        "perf".
>  
> +  edac-enabled:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description:
> +      A72 CPUs support Error Detection And Correction (EDAC) on their L1 and
> +      L2 caches. This flag marks this function as usable.
> +#    type: boolean

Drop

Rest looks fine to me, seems implementing Rob's comments.

With change above:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>

Best regards,
Krzysztof