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Message-ID: <b1f58f49-83b3-48c3-8c44-4c82fcd2f69b@genexis.eu>
Date: Wed, 28 May 2025 11:20:53 +0200
From: Benjamin Larsson <benjamin.larsson@...exis.eu>
To: Christian Marangi <ansuelsmth@...il.com>,
Lorenzo Bianconi <lorenzo@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Sean Wang <sean.wang@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
linux-mediatek@...ts.infradead.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 6/6] pinctrl: airoha: add support for Airoha AN7583 PINs
Hi.
On 28/05/2025 00:20, Christian Marangi wrote:
> Add all the required entry to add suppot for Airoha AN7583 PINs.
>
> Where possible the same function group are used from Airoha EN7581 to
> reduce code duplication.
>
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>
> ---
> drivers/pinctrl/mediatek/pinctrl-airoha.c | 733 ++++++++++++++++++++++
> 1 file changed, 733 insertions(+)
>
> diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> index 8c8d5b598f4f..0960649d5d66 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
> @@ -75,6 +75,7 @@
> #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
> #define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
> #define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
> +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
> #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
> #define GPIO_PCM_SPI_MODE_MASK BIT(16)
> #define GPIO_PCM2_MODE_MASK BIT(13)
Missing are the pinmuxes for the following:
{ RG_BCDR_FLUSH_EN, IOMUX3, 1<<28},
{ RG_GPIO_PON2_MODE, IOMUX3, 1<<27},
{ RG_MDIO_0_GPIO_MODE, IOMUX3, 1<<26},
{ RG_MDC_0_GPIO_MODE, IOMUX3, 1<<25},
{ RG_UART_RXD_GPIO_MODE, IOMUX3, 1<<24},
{ RG_UART_TXD_GPIO_MODE, IOMUX3, 1<<23},
{ RG_SPI_MISO_GPIO_MODE, IOMUX3, 1<<22},
{ RG_SPI_MOSI_GPIO_MODE, IOMUX3, 1<<21},
{ RG_SPI_CS_GPIO_MODE, IOMUX3, 1<<20},
{ RG_SPI_CLK_GPIO_MODE, IOMUX3, 1<<19},
{ RG_I2C1_SDA_GPIO_MODE, IOMUX3, 1<<18},
{ RG_I2C1_SCL_GPIO_MODE, IOMUX3, 1<<17},
{ RG_I2C0_SDA_GPIO_MODE, IOMUX3, 1<<16},
{ RG_I2C0_SCL_GPIO_MODE, IOMUX3, 1<<15},
> @@ -129,6 +130,8 @@
>
> /* CONF */
> #define REG_I2C_SDA_E2 0x001c
> +#define AN7583_I2C1_SCL_E2_MASK BIT(16)
> +#define AN7583_I2C1_SDA_E2_MASK BIT(15)
> #define SPI_MISO_E2_MASK BIT(14)
> #define SPI_MOSI_E2_MASK BIT(13)
> #define SPI_CLK_E2_MASK BIT(12)
> @@ -136,12 +139,16 @@
> #define PCIE2_RESET_E2_MASK BIT(10)
> #define PCIE1_RESET_E2_MASK BIT(9)
> #define PCIE0_RESET_E2_MASK BIT(8)
> +#define AN7583_MDIO_0_E2_MASK BIT(5)
> +#define AN7583_MDC_0_E2_MASK BIT(4)
> #define UART1_RXD_E2_MASK BIT(3)
> #define UART1_TXD_E2_MASK BIT(2)
> #define I2C_SCL_E2_MASK BIT(1)
> #define I2C_SDA_E2_MASK BIT(0)
>
> #define REG_I2C_SDA_E4 0x0020
> +#define AN7583_I2C1_SCL_E4_MASK BIT(16)
> +#define AN7583_I2C1_SDA_E4_MASK BIT(15)
> #define SPI_MISO_E4_MASK BIT(14)
> #define SPI_MOSI_E4_MASK BIT(13)
> #define SPI_CLK_E4_MASK BIT(12)
> @@ -149,6 +156,8 @@
> #define PCIE2_RESET_E4_MASK BIT(10)
> #define PCIE1_RESET_E4_MASK BIT(9)
> #define PCIE0_RESET_E4_MASK BIT(8)
> +#define AN7583_MDIO_0_E4_MASK BIT(5)
> +#define AN7583_MDC_0_E4_MASK BIT(4)
> #define UART1_RXD_E4_MASK BIT(3)
> #define UART1_TXD_E4_MASK BIT(2)
> #define I2C_SCL_E4_MASK BIT(1)
> @@ -160,6 +169,8 @@
> #define REG_GPIO_H_E4 0x0030
>
> #define REG_I2C_SDA_PU 0x0044
> +#define AN7583_I2C1_SCL_PU_MASK BIT(16)
> +#define AN7583_I2C1_SDA_PU_MASK BIT(15)
> #define SPI_MISO_PU_MASK BIT(14)
> #define SPI_MOSI_PU_MASK BIT(13)
> #define SPI_CLK_PU_MASK BIT(12)
> @@ -167,12 +178,16 @@
> #define PCIE2_RESET_PU_MASK BIT(10)
> #define PCIE1_RESET_PU_MASK BIT(9)
> #define PCIE0_RESET_PU_MASK BIT(8)
> +#define AN7583_MDIO_0_PU_MASK BIT(5)
> +#define AN7583_MDC_0_PU_MASK BIT(4)
> #define UART1_RXD_PU_MASK BIT(3)
> #define UART1_TXD_PU_MASK BIT(2)
> #define I2C_SCL_PU_MASK BIT(1)
> #define I2C_SDA_PU_MASK BIT(0)
>
> #define REG_I2C_SDA_PD 0x0048
> +#define AN7583_I2C1_SDA_PD_MASK BIT(16)
> +#define AN7583_I2C1_SCL_PD_MASK BIT(15)
> #define SPI_MISO_PD_MASK BIT(14)
> #define SPI_MOSI_PD_MASK BIT(13)
> #define SPI_CLK_PD_MASK BIT(12)
> @@ -180,6 +195,8 @@
> #define PCIE2_RESET_PD_MASK BIT(10)
> #define PCIE1_RESET_PD_MASK BIT(9)
> #define PCIE0_RESET_PD_MASK BIT(8)
> +#define AN7583_MDIO_0_PD_MASK BIT(5)
> +#define AN7583_MDC_0_PD_MASK BIT(4)
> #define UART1_RXD_PD_MASK BIT(3)
> #define UART1_TXD_PD_MASK BIT(2)
> #define I2C_SCL_PD_MASK BIT(1)
> @@ -627,10 +644,223 @@ static const struct pingroup en7581_pinctrl_groups[] = {
> PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
> };
>
> +static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
> + PINCTRL_PIN(2, "gpio0"),
> + PINCTRL_PIN(3, "gpio1"),
> + PINCTRL_PIN(4, "gpio2"),
> + PINCTRL_PIN(5, "gpio3"),
> + PINCTRL_PIN(6, "gpio4"),
> + PINCTRL_PIN(7, "gpio5"),
> + PINCTRL_PIN(8, "gpio6"),
> + PINCTRL_PIN(9, "gpio7"),
> + PINCTRL_PIN(10, "gpio8"),
> + PINCTRL_PIN(11, "gpio9"),
> + PINCTRL_PIN(12, "gpio10"),
> + PINCTRL_PIN(13, "gpio11"),
> + PINCTRL_PIN(14, "gpio12"),
> + PINCTRL_PIN(15, "gpio13"),
> + PINCTRL_PIN(16, "gpio14"),
> + PINCTRL_PIN(17, "gpio15"),
> + PINCTRL_PIN(18, "gpio16"),
> + PINCTRL_PIN(19, "gpio17"),
> + PINCTRL_PIN(20, "gpio18"),
> + PINCTRL_PIN(21, "gpio19"),
> + PINCTRL_PIN(22, "gpio20"),
> + PINCTRL_PIN(23, "gpio21"),
> + PINCTRL_PIN(24, "gpio22"),
> + PINCTRL_PIN(25, "gpio23"),
> + PINCTRL_PIN(26, "gpio24"),
> + PINCTRL_PIN(27, "gpio25"),
> + PINCTRL_PIN(28, "gpio26"),
> + PINCTRL_PIN(29, "gpio27"),
> + PINCTRL_PIN(30, "gpio28"),
> + PINCTRL_PIN(31, "gpio29"),
> + PINCTRL_PIN(32, "gpio30"),
> + PINCTRL_PIN(33, "gpio31"),
> + PINCTRL_PIN(34, "gpio32"),
> + PINCTRL_PIN(35, "gpio33"),
> + PINCTRL_PIN(36, "gpio34"),
> + PINCTRL_PIN(37, "gpio35"),
> + PINCTRL_PIN(38, "gpio36"),
> + PINCTRL_PIN(39, "gpio37"),
> + PINCTRL_PIN(40, "gpio38"),
> + PINCTRL_PIN(41, "i2c0_scl"),
> + PINCTRL_PIN(42, "i2c0_sda"),
> + PINCTRL_PIN(43, "i2c1_scl"),
> + PINCTRL_PIN(44, "i2c1_sda"),
> + PINCTRL_PIN(45, "spi_clk"),
> + PINCTRL_PIN(46, "spi_cs"),
> + PINCTRL_PIN(47, "spi_mosi"),
> + PINCTRL_PIN(48, "spi_miso"),
> + PINCTRL_PIN(49, "uart_txd"),
> + PINCTRL_PIN(50, "uart_rxd"),
> + PINCTRL_PIN(51, "pcie_reset0"),
> + PINCTRL_PIN(52, "pcie_reset1"),
> + PINCTRL_PIN(53, "mdc_0"),
> + PINCTRL_PIN(54, "mdio_0"),
> +};
> +
> +static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
I have other pin numbers listed in my documentation (my numbers align
with gpio number).
static const int pon_pins0[] = { 13, 14, 17, 18 };
static const int pon_pins1[] = { 36, 37, 38 };
static const int olt_pins0[] = { 34, 35, 36, 37, 38 };
MvH
Benjamin Larsson
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