linux-kernel - [PATCH] cxl/trace: Fix typo in macro and spec reference

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Message-ID: <20250531114317.3341757-1-alok.a.tiwari@oracle.com>
Date: Sat, 31 May 2025 04:41:58 -0700
From: Alok Tiwari <alok.a.tiwari@...cle.com>
To: dave@...olabs.net, jonathan.cameron@...wei.com, dave.jiang@...el.com,
        alison.schofield@...el.com, vishal.l.verma@...el.com,
        ira.weiny@...el.com, dan.j.williams@...el.com, shiju.jose@...wei.com,
        viro@...iv.linux.org.uk, Smita.KoralahalliChannabasappa@....com,
        fabio.m.de.francesco@...ux.intel.com, linux-cxl@...r.kernel.org
Cc: alok.a.tiwari@...cle.com, linux-kernel@...r.kernel.org,
        darren.kenny@...cle.com
Subject: [PATCH] cxl/trace: Fix typo in macro and spec reference

- Corrects a typo in the macro name: CXL_RAS_CE_RETRY_THRESH
was previously misspelled as CLX_RAS_CE_RETRY_THRESH.

- fixes a typo in a spec reference from "res" to "rev"
in the CXL spec reference: "CXL rev 3.1 section 8.2.9.2.1.3"

Signed-off-by: Alok Tiwari <alok.a.tiwari@...cle.com>
---
 drivers/cxl/core/trace.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index 25ebfbc1616c..de0712a31d96 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -109,7 +109,7 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
 #define CXL_RAS_CE_CACHE_DATA_ECC	BIT(0)
 #define CXL_RAS_CE_MEM_DATA_ECC		BIT(1)
 #define CXL_RAS_CE_CRC_THRESH		BIT(2)
-#define CLX_RAS_CE_RETRY_THRESH		BIT(3)
+#define CXL_RAS_CE_RETRY_THRESH		BIT(3)
 #define CXL_RAS_CE_CACHE_POISON		BIT(4)
 #define CXL_RAS_CE_MEM_POISON		BIT(5)
 #define CXL_RAS_CE_PHYS_LAYER_ERR	BIT(6)
@@ -118,7 +118,7 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
 	{ CXL_RAS_CE_CACHE_DATA_ECC, "Cache Data ECC Error" },			\
 	{ CXL_RAS_CE_MEM_DATA_ECC, "Memory Data ECC Error" },			\
 	{ CXL_RAS_CE_CRC_THRESH, "CRC Threshold Hit" },				\
-	{ CLX_RAS_CE_RETRY_THRESH, "Retry Threshold" },				\
+	{ CXL_RAS_CE_RETRY_THRESH, "Retry Threshold" },				\
 	{ CXL_RAS_CE_CACHE_POISON, "Received Cache Poison From Peer" },		\
 	{ CXL_RAS_CE_MEM_POISON, "Received Memory Poison From Peer" },		\
 	{ CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" }	\
@@ -684,7 +684,7 @@ TRACE_EVENT(cxl_dram,
 /*
  * Memory Module Event Record - MMER
  *
- * CXL res 3.1 section 8.2.9.2.1.3; Table 8-47
+ * CXL rev 3.1 section 8.2.9.2.1.3; Table 8-47
  */
 #define CXL_MMER_HEALTH_STATUS_CHANGE		0x00
 #define CXL_MMER_MEDIA_STATUS_CHANGE		0x01
-- 
2.47.1