linux-kernel - Re: [PATCH] mtd: nand: brcmnand: fix mtd corrected bits stat

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAA_RMS5xf7fmMWp_a0Jy_4Sd365gH=MBjS6bi4o7ocx43M61rA@mail.gmail.com>
Date: Sun, 1 Jun 2025 23:16:01 -0700
From: David Regan <dregan@...adcom.com>
To: Jonas Gorski <jonas.gorski@...il.com>
Cc: David Regan <dregan@...adcom.com>, 
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, linux-mtd@...ts.infradead.org, 
	bcm-kernel-feedback-list@...adcom.com, 
	William Zhang <william.zhang@...adcom.com>, Anand Gore <anand.gore@...adcom.com>, 
	Florian Fainelli <florian.fainelli@...adcom.com>, Kamal Dasu <kamal.dasu@...adcom.com>, 
	Dan Beygelman <dan.beygelman@...adcom.com>, Miquel Raynal <miquel.raynal@...tlin.com>, 
	Álvaro Fernández Rojas <noltari@...il.com>, 
	rafal@...ecki.pl, computersforpeace@...il.com, frieder.schrempf@...tron.de, 
	Vignesh Raghavendra <vigneshr@...com>, Richard Weinberger <richard@....at>, 
	Boris Brezillon <bbrezillon@...nel.org>, kdasu.kdev@...il.com, 
	JaimeLiao <jaimeliao.tw@...il.com>, Adam Borowski <kilobyte@...band.pl>, dgcbueu@...il.com, 
	dregan@...l.com
Subject: Re: [PATCH] mtd: nand: brcmnand: fix mtd corrected bits stat

Hi Jonas,

On Fri, May 30, 2025 at 1:27 AM Jonas Gorski <jonas.gorski@...il.com> wrote:
>
> Hi,
>
> On Fri, May 30, 2025 at 5:48 AM David Regan <dregan@...adcom.com> wrote:
> >
> > Currently we attempt to get the amount of flipped bits from a hardware
> > location which is reset on every subpage. Instead obtain total flipped
> > bits stat from hardware accumulator. In addition identify the correct
> > maximum subpage corrected bits.
> >
> > Signed-off-by: David Regan <dregan@...adcom.com>
> > Reviewed-by: William Zhang <william.zhang@...adcom.com>
> > Reviewed-by: Kamal Dasu <kamal.dasu@...adcom.com>
> > ---
> >  drivers/mtd/nand/raw/brcmnand/brcmnand.c | 48 ++++++++++++++++++------
> >  1 file changed, 37 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> > index 62bdda3be92f..43ab4aedda55 100644
> > --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> > +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> > @@ -361,6 +361,7 @@ enum brcmnand_reg {
> >         BRCMNAND_CORR_COUNT,
> >         BRCMNAND_CORR_EXT_ADDR,
> >         BRCMNAND_CORR_ADDR,
> > +       BRCMNAND_READ_ERROR_COUNT,
> >         BRCMNAND_UNCORR_EXT_ADDR,
> >         BRCMNAND_UNCORR_ADDR,
> >         BRCMNAND_SEMAPHORE,
> > @@ -389,6 +390,7 @@ static const u16 brcmnand_regs_v21[] = {
> >         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
> >         [BRCMNAND_UNCORR_COUNT]         =     0,
> >         [BRCMNAND_CORR_COUNT]           =     0,
> > +       [BRCMNAND_READ_ERROR_COUNT]     =     0,
> >         [BRCMNAND_CORR_EXT_ADDR]        =  0x60,
> >         [BRCMNAND_CORR_ADDR]            =  0x64,
> >         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x68,
> > @@ -419,6 +421,7 @@ static const u16 brcmnand_regs_v33[] = {
> >         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
> >         [BRCMNAND_UNCORR_COUNT]         =     0,
> >         [BRCMNAND_CORR_COUNT]           =     0,
> > +       [BRCMNAND_READ_ERROR_COUNT]     =     0,
> >         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
> >         [BRCMNAND_CORR_ADDR]            =  0x74,
> >         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
> > @@ -449,6 +452,7 @@ static const u16 brcmnand_regs_v50[] = {
> >         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
> >         [BRCMNAND_UNCORR_COUNT]         =     0,
> >         [BRCMNAND_CORR_COUNT]           =     0,
> > +       [BRCMNAND_READ_ERROR_COUNT]     =     0,
>
> I see this register in BCM63268's NAND controller at 0x80, which is a
> v4.x one, so I'm surprised v5.0 doesn't have it. Or does it not work
> there? I don't know if v3.3 also has it or if using this on v4.x would
> require a separate brcmnand_regs entry.

Thank you for pointing this out, I did just verify the register at offset
0x80 does appear to work correctly on my 63268. I'll put some update
in the next patch revision to reflect this.

>
> Can't really comment on the remaining changes.
>
> Regards,
> Jonas

-Dave