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Message-ID: <e602e789-2391-4812-bc2b-e3ef594b106e@nxsw.ie>
Date: Tue, 03 Jun 2025 08:05:51 +0000
From: Bryan O'Donoghue <bod.linux@...w.ie>
To: Jagadeesh Kona <quic_jkona@...cinc.com>, Bjorn Andersson <andersson@...nel.org>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>, Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>, Dmitry Baryshkov <lumag@...nel.org>
Cc: Ajit Pandey <quic_ajipan@...cinc.com>, Imran Shaik <quic_imrashai@...cinc.com>, Taniya Das <quic_tdas@...cinc.com>, Satya Priya Kakitapalli <quic_skakitap@...cinc.com>, linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, Bryan O'Donoghue <bryan.odonoghue@...aro.org>, Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>, Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v5 09/18] clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe
On 30/05/2025 14:20, Jagadeesh Kona wrote:
> Camera PLLs on SM8450/SM8475 require both MMCX and MXC rails to be
> kept ON to configure the PLLs properly. Hence move runtime power
> management, PLL configuration and enable critical clocks to
> qcom_cc_really_probe() which ensures all required power domains are in
> enabled state before configuring the PLLs or enabling the clocks.
>
> This change also removes the modelling for cam_cc_gdsc_clk and keeps it
> always ON from probe since using CLK_IS_CRITICAL will prevent the clock
> controller associated power domains from collapsing due to clock framework
> invoking clk_pm_runtime_get() during prepare.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> Signed-off-by: Jagadeesh Kona <quic_jkona@...cinc.com>
> ---
> drivers/clk/qcom/camcc-sm8450.c | 89 ++++++++++++++++++++---------------------
> 1 file changed, 44 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c
> index 08982737e4901c0703e19f8dd2d302e24748210c..4dd8be8cc9881c890d2e7c3a12f12816a9ab47dc 100644
> --- a/drivers/clk/qcom/camcc-sm8450.c
> +++ b/drivers/clk/qcom/camcc-sm8450.c
> @@ -86,6 +86,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll0_config = {
>
> static struct clk_alpha_pll cam_cc_pll0 = {
> .offset = 0x0,
> + .config = &cam_cc_pll0_config,
> .vco_table = lucid_evo_vco,
> .num_vco = ARRAY_SIZE(lucid_evo_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> @@ -191,6 +192,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll1_config = {
>
> static struct clk_alpha_pll cam_cc_pll1 = {
> .offset = 0x1000,
> + .config = &cam_cc_pll1_config,
> .vco_table = lucid_evo_vco,
> .num_vco = ARRAY_SIZE(lucid_evo_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> @@ -257,6 +259,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll2_config = {
>
> static struct clk_alpha_pll cam_cc_pll2 = {
> .offset = 0x2000,
> + .config = &cam_cc_pll2_config,
> .vco_table = rivian_evo_vco,
> .num_vco = ARRAY_SIZE(rivian_evo_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
> @@ -296,6 +299,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll3_config = {
>
> static struct clk_alpha_pll cam_cc_pll3 = {
> .offset = 0x3000,
> + .config = &cam_cc_pll3_config,
> .vco_table = lucid_evo_vco,
> .num_vco = ARRAY_SIZE(lucid_evo_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> @@ -368,6 +372,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll4_config = {
>
> static struct clk_alpha_pll cam_cc_pll4 = {
> .offset = 0x4000,
> + .config = &cam_cc_pll4_config,
> .vco_table = lucid_evo_vco,
> .num_vco = ARRAY_SIZE(lucid_evo_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> @@ -440,6 +445,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll5_config = {
>
> static struct clk_alpha_pll cam_cc_pll5 = {
> .offset = 0x5000,
> + .config = &cam_cc_pll5_config,
> .vco_table = lucid_evo_vco,
> .num_vco = ARRAY_SIZE(lucid_evo_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> @@ -512,6 +518,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll6_config = {
>
> static struct clk_alpha_pll cam_cc_pll6 = {
> .offset = 0x6000,
> + .config = &cam_cc_pll6_config,
> .vco_table = lucid_evo_vco,
> .num_vco = ARRAY_SIZE(lucid_evo_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> @@ -584,6 +591,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll7_config = {
>
> static struct clk_alpha_pll cam_cc_pll7 = {
> .offset = 0x7000,
> + .config = &cam_cc_pll7_config,
> .vco_table = lucid_evo_vco,
> .num_vco = ARRAY_SIZE(lucid_evo_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> @@ -656,6 +664,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll8_config = {
>
> static struct clk_alpha_pll cam_cc_pll8 = {
> .offset = 0x8000,
> + .config = &cam_cc_pll8_config,
> .vco_table = lucid_evo_vco,
> .num_vco = ARRAY_SIZE(lucid_evo_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> @@ -1476,24 +1485,6 @@ static struct clk_rcg2 cam_cc_xo_clk_src = {
> },
> };
>
> -static struct clk_branch cam_cc_gdsc_clk = {
> - .halt_reg = 0x1320c,
> - .halt_check = BRANCH_HALT,
> - .clkr = {
> - .enable_reg = 0x1320c,
> - .enable_mask = BIT(0),
> - .hw.init = &(const struct clk_init_data) {
> - .name = "cam_cc_gdsc_clk",
> - .parent_hws = (const struct clk_hw*[]) {
> - &cam_cc_xo_clk_src.clkr.hw,
> - },
> - .num_parents = 1,
> - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> static struct clk_branch cam_cc_bps_ahb_clk = {
> .halt_reg = 0x1004c,
> .halt_check = BRANCH_HALT,
> @@ -2819,7 +2810,6 @@ static struct clk_regmap *cam_cc_sm8450_clocks[] = {
> [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
> [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
> [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
> - [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
> [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
> [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
> [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
> @@ -2913,6 +2903,22 @@ static const struct qcom_reset_map cam_cc_sm8450_resets[] = {
> [CAM_CC_SFE_1_BCR] = { 0x13094 },
> };
>
> +static struct clk_alpha_pll *cam_cc_sm8450_plls[] = {
> + &cam_cc_pll0,
> + &cam_cc_pll1,
> + &cam_cc_pll2,
> + &cam_cc_pll3,
> + &cam_cc_pll4,
> + &cam_cc_pll5,
> + &cam_cc_pll6,
> + &cam_cc_pll7,
> + &cam_cc_pll8,
> +};
> +
> +static u32 cam_cc_sm8450_critical_cbcrs[] = {
> + 0x1320c, /* CAM_CC_GDSC_CLK */
> +};
> +
> static const struct regmap_config cam_cc_sm8450_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> @@ -3021,6 +3027,13 @@ static struct gdsc *cam_cc_sm8450_gdscs[] = {
> [TITAN_TOP_GDSC] = &titan_top_gdsc,
> };
>
> +static struct qcom_cc_driver_data cam_cc_sm8450_driver_data = {
> + .alpha_plls = cam_cc_sm8450_plls,
> + .num_alpha_plls = ARRAY_SIZE(cam_cc_sm8450_plls),
> + .clk_cbcrs = cam_cc_sm8450_critical_cbcrs,
> + .num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8450_critical_cbcrs),
> +};
> +
> static const struct qcom_cc_desc cam_cc_sm8450_desc = {
> .config = &cam_cc_sm8450_regmap_config,
> .clks = cam_cc_sm8450_clocks,
> @@ -3029,6 +3042,8 @@ static const struct qcom_cc_desc cam_cc_sm8450_desc = {
> .num_resets = ARRAY_SIZE(cam_cc_sm8450_resets),
> .gdscs = cam_cc_sm8450_gdscs,
> .num_gdscs = ARRAY_SIZE(cam_cc_sm8450_gdscs),
> + .use_rpm = true,
> + .driver_data = &cam_cc_sm8450_driver_data,
> };
>
> static const struct of_device_id cam_cc_sm8450_match_table[] = {
> @@ -3040,12 +3055,6 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table);
>
> static int cam_cc_sm8450_probe(struct platform_device *pdev)
> {
> - struct regmap *regmap;
> -
> - regmap = qcom_cc_map(pdev, &cam_cc_sm8450_desc);
> - if (IS_ERR(regmap))
> - return PTR_ERR(regmap);
> -
> if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) {
> /* Update CAMCC PLL0 */
> cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
> @@ -3092,28 +3101,18 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev)
> cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
> cam_cc_pll8_out_even.clkr.hw.init = &sm8475_cam_cc_pll8_out_even_init;
>
> - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &sm8475_cam_cc_pll0_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &sm8475_cam_cc_pll1_config);
> - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &sm8475_cam_cc_pll2_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &sm8475_cam_cc_pll3_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &sm8475_cam_cc_pll4_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &sm8475_cam_cc_pll5_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &sm8475_cam_cc_pll6_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &sm8475_cam_cc_pll7_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &sm8475_cam_cc_pll8_config);
> - } else {
> - clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
> - clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
> - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
> - clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
> - clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
> - clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
> - clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
> - clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
> - clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
> + cam_cc_pll0.config = &sm8475_cam_cc_pll0_config;
> + cam_cc_pll1.config = &sm8475_cam_cc_pll1_config;
> + cam_cc_pll2.config = &sm8475_cam_cc_pll2_config;
> + cam_cc_pll3.config = &sm8475_cam_cc_pll3_config;
> + cam_cc_pll4.config = &sm8475_cam_cc_pll4_config;
> + cam_cc_pll5.config = &sm8475_cam_cc_pll5_config;
> + cam_cc_pll6.config = &sm8475_cam_cc_pll6_config;
> + cam_cc_pll7.config = &sm8475_cam_cc_pll7_config;
> + cam_cc_pll8.config = &sm8475_cam_cc_pll8_config;
> }
>
> - return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap);
> + return qcom_cc_probe(pdev, &cam_cc_sm8450_desc);
> }
>
> static struct platform_driver cam_cc_sm8450_driver = {
>
> --
> 2.34.1
>
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
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