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Message-ID: <db1827ed-4710-48ba-8037-3888957b06e9@nxsw.ie>
Date: Tue, 03 Jun 2025 08:06:28 +0000
From: Bryan O'Donoghue <bod.linux@...w.ie>
To: Jagadeesh Kona <quic_jkona@...cinc.com>, Bjorn Andersson <andersson@...nel.org>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>, Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>, Dmitry Baryshkov <lumag@...nel.org>
Cc: Ajit Pandey <quic_ajipan@...cinc.com>, Imran Shaik <quic_imrashai@...cinc.com>, Taniya Das <quic_tdas@...cinc.com>, Satya Priya Kakitapalli <quic_skakitap@...cinc.com>, linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, Bryan O'Donoghue <bryan.odonoghue@...aro.org>, Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>, Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v5 10/18] clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe
On 30/05/2025 14:20, Jagadeesh Kona wrote:
> Camera PLLs on SM8550 require both MMCX and MXC rails to be kept ON to
> configure the PLLs properly. Hence move runtime power management, PLL
> configuration and enabling critical clocks to qcom_cc_really_probe() which
> ensures all required power domains are in enabled state before configuring
> the PLLs or enabling the clocks.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> Signed-off-by: Jagadeesh Kona <quic_jkona@...cinc.com>
> ---
> drivers/clk/qcom/camcc-sm8550.c | 85 +++++++++++++++++++++--------------------
> 1 file changed, 44 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
> index 871155783c798fd9245d735642272eae2a2d3465..63aed9e4c362d523093409f74ef4e57f292ddf90 100644
> --- a/drivers/clk/qcom/camcc-sm8550.c
> +++ b/drivers/clk/qcom/camcc-sm8550.c
> @@ -7,7 +7,6 @@
> #include <linux/mod_devicetable.h>
> #include <linux/module.h>
> #include <linux/platform_device.h>
> -#include <linux/pm_runtime.h>
> #include <linux/regmap.h>
>
> #include <dt-bindings/clock/qcom,sm8550-camcc.h>
> @@ -74,6 +73,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = {
>
> static struct clk_alpha_pll cam_cc_pll0 = {
> .offset = 0x0,
> + .config = &cam_cc_pll0_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -151,6 +151,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = {
>
> static struct clk_alpha_pll cam_cc_pll1 = {
> .offset = 0x1000,
> + .config = &cam_cc_pll1_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -201,6 +202,7 @@ static const struct alpha_pll_config cam_cc_pll2_config = {
>
> static struct clk_alpha_pll cam_cc_pll2 = {
> .offset = 0x2000,
> + .config = &cam_cc_pll2_config,
> .vco_table = rivian_ole_vco,
> .num_vco = ARRAY_SIZE(rivian_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
> @@ -232,6 +234,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = {
>
> static struct clk_alpha_pll cam_cc_pll3 = {
> .offset = 0x3000,
> + .config = &cam_cc_pll3_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -286,6 +289,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = {
>
> static struct clk_alpha_pll cam_cc_pll4 = {
> .offset = 0x4000,
> + .config = &cam_cc_pll4_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -340,6 +344,7 @@ static const struct alpha_pll_config cam_cc_pll5_config = {
>
> static struct clk_alpha_pll cam_cc_pll5 = {
> .offset = 0x5000,
> + .config = &cam_cc_pll5_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -394,6 +399,7 @@ static const struct alpha_pll_config cam_cc_pll6_config = {
>
> static struct clk_alpha_pll cam_cc_pll6 = {
> .offset = 0x6000,
> + .config = &cam_cc_pll6_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -448,6 +454,7 @@ static const struct alpha_pll_config cam_cc_pll7_config = {
>
> static struct clk_alpha_pll cam_cc_pll7 = {
> .offset = 0x7000,
> + .config = &cam_cc_pll7_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -502,6 +509,7 @@ static const struct alpha_pll_config cam_cc_pll8_config = {
>
> static struct clk_alpha_pll cam_cc_pll8 = {
> .offset = 0x8000,
> + .config = &cam_cc_pll8_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -556,6 +564,7 @@ static const struct alpha_pll_config cam_cc_pll9_config = {
>
> static struct clk_alpha_pll cam_cc_pll9 = {
> .offset = 0x9000,
> + .config = &cam_cc_pll9_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -610,6 +619,7 @@ static const struct alpha_pll_config cam_cc_pll10_config = {
>
> static struct clk_alpha_pll cam_cc_pll10 = {
> .offset = 0xa000,
> + .config = &cam_cc_pll10_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -664,6 +674,7 @@ static const struct alpha_pll_config cam_cc_pll11_config = {
>
> static struct clk_alpha_pll cam_cc_pll11 = {
> .offset = 0xb000,
> + .config = &cam_cc_pll11_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -718,6 +729,7 @@ static const struct alpha_pll_config cam_cc_pll12_config = {
>
> static struct clk_alpha_pll cam_cc_pll12 = {
> .offset = 0xc000,
> + .config = &cam_cc_pll12_config,
> .vco_table = lucid_ole_vco,
> .num_vco = ARRAY_SIZE(lucid_ole_vco),
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -3479,6 +3491,27 @@ static const struct qcom_reset_map cam_cc_sm8550_resets[] = {
> [CAM_CC_SFE_1_BCR] = { 0x133dc },
> };
>
> +static struct clk_alpha_pll *cam_cc_sm8550_plls[] = {
> + &cam_cc_pll0,
> + &cam_cc_pll1,
> + &cam_cc_pll2,
> + &cam_cc_pll3,
> + &cam_cc_pll4,
> + &cam_cc_pll5,
> + &cam_cc_pll6,
> + &cam_cc_pll7,
> + &cam_cc_pll8,
> + &cam_cc_pll9,
> + &cam_cc_pll10,
> + &cam_cc_pll11,
> + &cam_cc_pll12,
> +};
> +
> +static u32 cam_cc_sm8550_critical_cbcrs[] = {
> + 0x1419c, /* CAM_CC_GDSC_CLK */
> + 0x142cc, /* CAM_CC_SLEEP_CLK */
> +};
> +
> static const struct regmap_config cam_cc_sm8550_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> @@ -3487,6 +3520,13 @@ static const struct regmap_config cam_cc_sm8550_regmap_config = {
> .fast_io = true,
> };
>
> +static struct qcom_cc_driver_data cam_cc_sm8550_driver_data = {
> + .alpha_plls = cam_cc_sm8550_plls,
> + .num_alpha_plls = ARRAY_SIZE(cam_cc_sm8550_plls),
> + .clk_cbcrs = cam_cc_sm8550_critical_cbcrs,
> + .num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8550_critical_cbcrs),
> +};
> +
> static const struct qcom_cc_desc cam_cc_sm8550_desc = {
> .config = &cam_cc_sm8550_regmap_config,
> .clks = cam_cc_sm8550_clocks,
> @@ -3495,6 +3535,8 @@ static const struct qcom_cc_desc cam_cc_sm8550_desc = {
> .num_resets = ARRAY_SIZE(cam_cc_sm8550_resets),
> .gdscs = cam_cc_sm8550_gdscs,
> .num_gdscs = ARRAY_SIZE(cam_cc_sm8550_gdscs),
> + .use_rpm = true,
> + .driver_data = &cam_cc_sm8550_driver_data,
> };
>
> static const struct of_device_id cam_cc_sm8550_match_table[] = {
> @@ -3505,46 +3547,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8550_match_table);
>
> static int cam_cc_sm8550_probe(struct platform_device *pdev)
> {
> - struct regmap *regmap;
> - int ret;
> -
> - ret = devm_pm_runtime_enable(&pdev->dev);
> - if (ret)
> - return ret;
> -
> - ret = pm_runtime_resume_and_get(&pdev->dev);
> - if (ret)
> - return ret;
> -
> - regmap = qcom_cc_map(pdev, &cam_cc_sm8550_desc);
> - if (IS_ERR(regmap)) {
> - pm_runtime_put(&pdev->dev);
> - return PTR_ERR(regmap);
> - }
> -
> - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
> - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config);
> - clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config);
> -
> - /* Keep some clocks always-on */
> - qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */
> - qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */
> -
> - ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8550_desc, regmap);
> -
> - pm_runtime_put(&pdev->dev);
> -
> - return ret;
> + return qcom_cc_probe(pdev, &cam_cc_sm8550_desc);
> }
>
> static struct platform_driver cam_cc_sm8550_driver = {
>
> --
> 2.34.1
>
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
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