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Message-ID: <2fb1965b-bef9-4a8e-a1c7-c8a77d957b23@linaro.org>
Date: Tue, 3 Jun 2025 10:50:23 +0100
From: James Clark <james.clark@...aro.org>
To: Marc Zyngier <maz@...nel.org>
Cc: Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>,
Mark Rutland <mark.rutland@....com>, Jonathan Corbet <corbet@....net>,
Oliver Upton <oliver.upton@...ux.dev>, Joey Gouly <joey.gouly@....com>,
Suzuki K Poulose <suzuki.poulose@....com>, Zenghui Yu
<yuzenghui@...wei.com>, Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo <acme@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>, Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org, linux-doc@...r.kernel.org,
kvmarm@...ts.linux.dev
Subject: Re: [PATCH v2 06/11] KVM: arm64: Add trap configs for PMSDSFR_EL1
On 29/05/2025 5:56 pm, Marc Zyngier wrote:
> On Thu, 29 May 2025 12:30:27 +0100,
> James Clark <james.clark@...aro.org> wrote:
>>
>> SPE data source filtering (SPE_FEAT_FDS) adds a new register
>> PMSDSFR_EL1, add the trap configs for it.
>>
>> Signed-off-by: James Clark <james.clark@...aro.org>
>> ---
>> arch/arm64/kvm/emulate-nested.c | 1 +
>> arch/arm64/kvm/sys_regs.c | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
>> index 0fcfcc0478f9..05d3e6b93ae9 100644
>> --- a/arch/arm64/kvm/emulate-nested.c
>> +++ b/arch/arm64/kvm/emulate-nested.c
>> @@ -1169,6 +1169,7 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
>> SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS),
>> SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS),
>> SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS),
>> + SR_TRAP(SYS_PMSDSFR_EL1, CGT_MDCR_TPMS),
>> SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF),
>> SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB),
>> SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB),
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 5dde9285afc8..9f544ac7b5a6 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -2956,6 +2956,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>> { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
>> { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
>> { SYS_DESC(SYS_PMBSR_EL1), undef_access },
>> + { SYS_DESC(SYS_PMSDSFR_EL1), undef_access },
>
> PMSDSFR_EL1 has an offset in the VNCR page (0x858), and must be
> described as such. This is equally true for a bunch of other
> SPE-related registers, so you might as well fix those while you're at
> it.
>
> Thanks,
>
> M.
>
I got a bit stuck with what that would look like with registers that are
only undef in case there was something that I missed, but do I just
document the offsets?
+++ b/arch/arm64/include/asm/vncr_mapping.h
@@ -87,6 +87,8 @@
#define VNCR_PMSICR_EL1 0x838
#define VNCR_PMSIRR_EL1 0x840
#define VNCR_PMSLATFR_EL1 0x848
+#define VNCR_PMSNEVFR_EL1 0x850
+#define VNCR_PMSDSFR_EL1 0x858
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -596,6 +596,16 @@ enum vcpu_sysreg {
VNCR(ICH_HCR_EL2),
VNCR(ICH_VMCR_EL2),
+ /* SPE Registers */
+ VNCR(PMBLIMITR_EL1),
+ VNCR(PMBPTR_EL1),
+ VNCR(PMBSR_EL1),
+ VNCR(PMSCR_EL1),
+ VNCR(PMSEVFR_EL1),
+ VNCR(PMSICR_EL1),
+ VNCR(PMSIRR_EL1),
+ VNCR(PMSLATFR_EL1),
And then sys_reg_descs[] remain as "{ SYS_DESC(SYS_PMBLIMITR_EL1),
undef_access }," rather than EL2_REG_VNCR() because we don't actually
want to change to bad_vncr_trap()?
There are some other parts about fine grained traps and res0 bits for
NV, but they all already look to be setup correctly. Except
HDFGRTR2_EL2.nPMSDSFR_EL1, but it's inverted, none of the FGT2 traps are
configured currently and PMSDSFR_EL1 is already trapped by MDCR_EL2 anyway.
Thanks
James
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