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Message-Id: <20250604091946.1890602-3-quic_ziyuzhan@quicinc.com>
Date: Wed, 4 Jun 2025 17:19:46 +0800
From: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
To: lpieralisi@...nel.org, kwilczynski@...nel.org,
manivannan.sadhasivam@...aro.org, robh@...nel.org, bhelgaas@...gle.com,
krzk+dt@...nel.org, neil.armstrong@...aro.org, abel.vesa@...aro.org,
kw@...ux.com, conor+dt@...nel.org, vkoul@...nel.org, kishon@...nel.org,
andersson@...nel.org, konradybcio@...nel.org
Cc: linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, quic_qianyu@...cinc.com,
Ziyue Zhang <quic_ziyuzhan@...cinc.com>,
Qiang Yu <qiang.yu@....qualcomm.com>
Subject: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset properties
Add PCIe lane equalization preset properties with all values set to 5 for
8 GT/s and 16 GT/s data rates to enhance link stability.
Co-developed-by: Qiang Yu <qiang.yu@....qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 45f536633f64..cc5c71891e8b 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -7159,6 +7159,10 @@ pcie0: pcie@...0000 {
phys = <&pcie0_phy>;
phy-names = "pciephy";
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
+ 0x5555 0x5555 0x5555 0x5555>;
+ eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
+
status = "disabled";
pcieport0: pcie@0 {
@@ -7317,6 +7321,10 @@ pcie1: pcie@...0000 {
phys = <&pcie1_phy>;
phy-names = "pciephy";
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
+ 0x5555 0x5555 0x5555 0x5555>;
+ eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
+
status = "disabled";
pcie@0 {
--
2.34.1
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