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Message-Id: <20250604091946.1890602-1-quic_ziyuzhan@quicinc.com>
Date: Wed, 4 Jun 2025 17:19:44 +0800
From: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
To: lpieralisi@...nel.org, kwilczynski@...nel.org,
manivannan.sadhasivam@...aro.org, robh@...nel.org, bhelgaas@...gle.com,
krzk+dt@...nel.org, neil.armstrong@...aro.org, abel.vesa@...aro.org,
kw@...ux.com, conor+dt@...nel.org, vkoul@...nel.org, kishon@...nel.org,
andersson@...nel.org, konradybcio@...nel.org
Cc: linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, quic_qianyu@...cinc.com,
Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Subject: [PATCH v1 0/2] Add Equalization Settings for 8.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0 GT/s and 16.0 GT/s
This series adds add equalization settings for 8.0 GT/s, and add PCIe lane equalization
preset properties for 8.0 GT/s and 16.0 GT/s for sa8775p ride platform, which fix AER
errors.
While equalization settings for 16 GT/s have already been set, this update adds the
required equalization settings for PCIe operating at 8.0 GT/s, including the
configuration of shadow registers, ensuring optimal performance and stability.
The DT change for sa8775p add PCIe lane equalization preset properties for 8 GT/s
and 16 GT/s data rates used in lane equalization procedure.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Ziyue Zhang (2):
PCI: qcom: Add equalization settings for 8.0 GT/s
arm64: dts: qcom: sa8775p: Add PCIe lane equalization preset
properties
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 8 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 -
drivers/pci/controller/dwc/pcie-qcom-common.c | 55 ++++++++++---------
drivers/pci/controller/dwc/pcie-qcom-common.h | 2 +-
drivers/pci/controller/dwc/pcie-qcom.c | 3 +-
5 files changed, 40 insertions(+), 29 deletions(-)
base-commit: 911483b25612c8bc32a706ba940738cc43299496
--
2.34.1
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