lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <aEXshsLK0JLUp37s@smile.fi.intel.com>
Date: Sun, 8 Jun 2025 23:03:18 +0300
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Jonathan Cameron <jic23@...nel.org>
Cc: Gustavo Silva <gustavograzs@...il.com>,
	Alex Lanzano <lanzano.alex@...il.com>,
	David Lechner <dlechner@...libre.com>,
	Nuno Sá <nuno.sa@...log.com>,
	linux-iio@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/3] iio: imu: bmi270: add channel for step counter

On Sat, Jun 07, 2025 at 04:50:04PM +0100, Jonathan Cameron wrote:
> On Fri, 6 Jun 2025 12:14:44 +0300
> Andy Shevchenko <andriy.shevchenko@...ux.intel.com> wrote:
> > On Thu, Jun 05, 2025 at 07:05:01PM -0300, Gustavo Silva wrote:

...

> > > +	set_mask_bits(&regval, mask, val);  
> > 
> > You can't do this on the 16-bit values on some architectures.
> > Maybe it's easy to implement cmpxchg() for 16-bit values there,
> > though.
> 
> It doesn't need to be atomic, so stick to traditional
> 
> 	regval &= ~mask;
> 	regval |= bits;
> 
> And avoid the fun of architectural corner cases entirely.

Standard pattern is

	regval = (regval & ~mask) | (val & mask);

this will be robust against any changes in the val.

-- 
With Best Regards,
Andy Shevchenko



Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ