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Message-ID: <20250609111448.GI8020@e132581.arm.com>
Date: Mon, 9 Jun 2025 12:14:48 +0100
From: Leo Yan <leo.yan@....com>
To: James Clark <james.clark@...aro.org>
Cc: Suzuki K Poulose <suzuki.poulose@....com>,
Mike Leach <mike.leach@...aro.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Marc Zyngier <maz@...nel.org>, coresight@...ts.linaro.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] coresight: trbe: Add ISB after TRBLIMITR write
On Mon, Jun 09, 2025 at 11:19:05AM +0100, James Clark wrote:
> DEN0154 states that hardware will be allowed to ignore writes to TRB*
> registers while the trace buffer is enabled. Add an ISB to ensure that
> it's disabled before clearing the other registers.
>
> This is purely defensive because it's expected that arm_trbe_disable()
> would be called before teardown which has the required ISB.
>
> Fixes: a2b579c41fe9 ("coresight: trbe: Remove redundant disable call")
> Signed-off-by: James Clark <james.clark@...aro.org>
Reviewed-by: Leo Yan <leo.yan@....com>
> ---
> drivers/hwtracing/coresight/coresight-trbe.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 8267dd1a2130..10f3fb401edf 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -257,6 +257,7 @@ static void trbe_drain_and_disable_local(struct trbe_cpudata *cpudata)
> static void trbe_reset_local(struct trbe_cpudata *cpudata)
> {
> write_sysreg_s(0, SYS_TRBLIMITR_EL1);
> + isb();
> trbe_drain_buffer();
> write_sysreg_s(0, SYS_TRBPTR_EL1);
> write_sysreg_s(0, SYS_TRBBASER_EL1);
>
> ---
> base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
> change-id: 20250609-james-cs-trblimitr-isb-523f20d874d6
>
> Best regards,
> --
> James Clark <james.clark@...aro.org>
>
> _______________________________________________
> CoreSight mailing list -- coresight@...ts.linaro.org
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