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Message-ID: <a5cf65a2179ffe0349bb1c24fb468f059aa2e763.camel@phytec.de>
Date: Wed, 11 Jun 2025 11:55:33 +0000
From: Yannic Moog <Y.Moog@...tec.de>
To: Shawn Guo <shawnguo2@...h.net>
CC: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>, Sascha
Hauer <s.hauer@...gutronix.de>, Pengutronix Kernel Team
<kernel@...gutronix.de>, Fabio Estevam <festevam@...il.com>, Catalin Marinas
<catalin.marinas@....com>, Will Deacon <will@...nel.org>,
"upstream@...ts.phytec.de" <upstream@...ts.phytec.de>, Benjamin Hahn
<B.Hahn@...tec.de>, Teresa Remmet <T.Remmet@...tec.de>, Yashwanth Varakala
<Y.Varakala@...tec.de>, Jan Remmet <J.Remmet@...tec.de>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"imx@...ts.linux.dev" <imx@...ts.linux.dev>,
"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2 2/2] arm64: dts: add imx95-libra-rdk-fpsc board
Hi Shawn,
Am Mittwoch, dem 11.06.2025 um 17:55 +0800 schrieb Shawn Guo:
> On Fri, May 09, 2025 at 02:15:51PM +0200, Yannic Moog wrote:
> > Add device tree for the Libra-i.MX 95 FPSC board. The Libra is a
> > pure development board and has hardware to support FPSC-24-A.0 set of
> > features. The phyCORE-i.MX 95 FPSC [1] SoM uses only a subset of
> > the hardware features of the Libra board. The phyCORE-i.MX 95 FPSC
> > itself is a System on Module designed around the i.MX 95 SoC.
> > The SoM and board utilize the Future Proof Solder Core [2] BGA standard
> > to connect to each other.
> >
> > To be able to easily map FPSC interface names to SoC interfaces, the
> > FPSC interface names are added as inline comments. Example:
> >
> > &lpi2c5 { /* I2C2 */
> > pinctrl-0 = <&pinctrl_lpi2c5>;
> > [...]
> > };
> >
> > Here, I2C2 is the FPSC interface name. The lpi2c5 instance of the i.MX 95
> > SoC is used to fulfill the i2c functionality and its signals are routed
> > to the FPSC I2C2 signal pins:
> >
> > pinctrl_lpi2c5: lpi2c5grp {
> > fsl,pins = <
> > IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e /*
> > I2C2_SDA */
> > IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e /* I2C2_SCL
> > */
> > >;
> > };
> >
> > [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-95-fpsc/
> > [2] https://www.phytec.eu/en/produkte/system-on-modules/fpsc/
> >
> > Signed-off-by: Yannic Moog <y.moog@...tec.de>
> > ---
> > arch/arm64/boot/dts/freescale/Makefile | 1 +
> > .../boot/dts/freescale/imx95-libra-rdk-fpsc.dts | 327 ++++++++++
> > .../boot/dts/freescale/imx95-phycore-fpsc.dtsi | 656
> > +++++++++++++++++++++
>
> > fitImage | Bin 0 -> 14928380
> > bytes
> > fitImage.its | 1 +
>
> What are these?
build artifacts I accidentally added to git. Will remove in next version.
>
> > 5 files changed, 985 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> > b/arch/arm64/boot/dts/freescale/Makefile
> > index 90652292a911..6d018d046009 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -325,6 +325,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb
> > imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo
> > imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo
> > dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-
> > pcie1-ep.dtb
> > +dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb
> >
> > imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-
> > kontron-dl.dtbo
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts
> > b/arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts
> > new file mode 100644
> > index 000000000000..adaa7429681f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts
> > @@ -0,0 +1,327 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright 2025 PHYTEC Messtechnik GmbH
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/leds/leds-pca9532.h>
> > +#include <dt-bindings/pwm/pwm.h>
> > +
> > +#include "imx95-phycore-fpsc.dtsi"
> > +
> > +/ {
> > + compatible = "phytec,imx95-libra-rdk-fpsc",
> > + "phytec,imx95-phycore-fpsc", "fsl,imx95";
> > + model = "PHYTEC Libra i.MX95 RDK FPSC";
> > +
> > + aliases {
> > + ethernet0 = &enetc_port0;
> > + serial0 = &lpuart7;
> > + serial1 = &lpuart8;
> > + can1 = &flexcan2;
> > + can2 = &flexcan1;
>
> Can we sort them alphabetically?
Will do
>
> > + };
> > +
> > + backlight_lvds0: backlight0 {
> > + compatible = "pwm-backlight";
> > + pinctrl-0 = <&pinctrl_lvds0>;
> > + power-supply = <®_vdd_12v0>;
> > + status = "disabled";
> > + };
> > +
> > + transceiver1: can-phy {
> > + compatible = "ti,tcan1043";
> > + #phy-cells = <0>;
> > + max-bitrate = <8000000>;
> > + enable-gpios = <&gpio_expander 10 GPIO_ACTIVE_LOW>;
> > + };
> > +
> > + transceiver2: can-phy {
> > + compatible = "ti,tcan1043";
> > + #phy-cells = <0>;
> > + max-bitrate = <8000000>;
> > + enable-gpios = <&gpio_expander 9 GPIO_ACTIVE_LOW>;
> > + };
> > +
> > + chosen {
> > + stdout-path = &lpuart7;
> > + };
>
> We usually put this generic node before devices.
I believe the script suggested to me by Frank told me to put it here. Will move
back to usual position.
>
> > +
> > + panel0_lvds: panel-lvds0 {
> > + backlight = <&backlight_lvds0>;
> > + power-supply = <®_vdd_3v3>;
> > + status = "disabled";
> > +
>
> Unneeded newline.
>
> > + };
> > +
> > + reg_vdd_12v0: regulator-vdd-12v0 {
> > + compatible = "regulator-fixed";
> > + regulator-always-on;
> > + regulator-boot-on;
> > + regulator-max-microvolt = <12000000>;
> > + regulator-min-microvolt = <12000000>;
> > + regulator-name = "VDD_12V0";
> > + };
> > +
> > + reg_vdd_1v8: regulator-vdd-1v8 {
> > + compatible = "regulator-fixed";
> > + regulator-always-on;
> > + regulator-boot-on;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-name = "VDD_1V8";
> > + };
> > +
> > + reg_vdd_3v3: regulator-vdd-3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-always-on;
> > + regulator-boot-on;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-name = "VDD_3V3";
> > + };
> > +
> > + reg_vdd_5v0: regulator-vdd-5v0 {
> > + compatible = "regulator-fixed";
> > + regulator-always-on;
> > + regulator-boot-on;
> > + regulator-max-microvolt = <5000000>;
> > + regulator-min-microvolt = <5000000>;
> > + regulator-name = "VDD_5V0";
> > + };
> > +};
> > +
> > +&enetc_port0 {
> > + phy-handle = <ðphy0>;
> > + status = "okay";
> > +};
> > +
> > +&enetc_port2 {
> > + managed = "in-band-status";
> > + phy-handle = <ðphy2>;
> > + phy-mode = "10gbase-r";
> > +};
> > +
> > +/* CAN FD */
> > +&flexcan1 {
> > + phys = <&transceiver1>;
> > + status = "okay";
> > +};
> > +
> > +&flexcan2 {
> > + phys = <&transceiver2>;
> > + status = "okay";
> > +};
> > +
> > +/* SPI-NOR */
> > +&flexspi1 {
> > + pinctrl-0 = <&pinctrl_flexspi>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +
> > + spi_nor: flash@0 {
> > + compatible = "jedec,spi-nor";
> > + reg = <0>;
> > + spi-max-frequency = <166000000>;
> > + spi-rx-bus-width = <4>;
> > + spi-tx-bus-width = <4>;
> > + vcc-supply = <®_vdd_1v8>;
> > + };
> > +};
> > +
> > +&gpio2 {
> > + gpio-line-names = "", "", "", "", "",
> > + "", "", "", "", "",
> > + "", "", "", "", "",
> > + "", "RGMII2_nINT", "GPIO4", "RTC_INT", "",
> > + "LVDS1_BL_EN";
> > +};
> > +
> > +&lpi2c1 {
> > + temperature-sensor@4f {
> > + compatible = "nxp,p3t1755";
> > + reg = <0x4f>;
> > + vs-supply = <®_vdd_1v8>;
> > + };
> > +};
> > +
> > +&lpi2c3 {
> > + status = "okay";
> > +
> > + leds@62 {
> > + compatible = "nxp,pca9533";
> > + reg = <0x62>;
> > +
> > + led-1 {
> > + type = <PCA9532_TYPE_LED>;
> > + };
> > +
> > + led-2 {
> > + type = <PCA9532_TYPE_LED>;
> > + };
> > +
> > + led-3 {
> > + type = <PCA9532_TYPE_LED>;
> > + };
> > + };
> > +};
> > +
> > +&lpi2c4 {
> > + status = "okay";
> > +
> > + gpio_expander: gpio@20 {
> > + compatible = "ti,tca6416";
> > + reg = <0x20>;
> > + interrupt-parent = <&gpio2>;
> > + interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
> > + #gpio-cells = <2>;
> > + gpio-controller;
> > + gpio-line-names = "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3",
> > + "CSI1_CTRL4", "CSI2_CTRL1", "CSI2_CTRL2",
> > + "CSI2_CTRL3", "CSI2_CTRL4", "CLK_EN_AV",
> > + "nCAN2_EN", "nCAN1_EN", "PCIE1_nWAKE",
> > + "PCIE2_nWAKE", "PCIE2_nALERT_3V3",
> > + "UART1_BT_RS_SEL", "UART1_RS232_485_SEL";
> > + vcc-supply = <®_vdd_1v8>;
> > +
> > + uart1_bt_rs_sel: bt-rs-hog {
> > + gpios = <14 GPIO_ACTIVE_HIGH>;
> > + gpio-hog;
> > + line-name = "UART1_BT_RS_SEL";
> > + output-low;
> > + };
> > +
> > + uart1_rs232_485_sel: rs232-485-hog {
> > + gpios = <15 GPIO_ACTIVE_HIGH>;
> > + gpio-hog;
> > + line-name = "UART1_RS232_485_SEL";
> > + output-low;
> > + };
> > + };
> > +};
> > +
> > +&lpi2c5 {
> > + status = "okay";
> > +
> > + eeprom@51 {
> > + compatible = "atmel,24c02";
> > + reg = <0x51>;
> > + pagesize = <16>;
> > + vcc-supply = <®_vdd_1v8>;
> > + };
> > +
>
> Unneeded newline.
>
> > +};
> > +
> > +/* Used for M33 debug */
> > +&lpuart2 {
> > + pinctrl-0 = <&pinctrl_lpuart2>;
> > + pinctrl-names = "default";
> > +};
> > +
> > +/* A-55 debug UART */
> > +&lpuart7 {
> > + status = "okay";
> > +};
> > +
> > +/* RS232/RS485/BT */
> > +&lpuart8 {
> > + uart-has-rtscts;
> > + status = "okay";
> > +};
> > +
> > +&netc_emdio { /* RGMII2 */
> > + ethphy0: ethernet-phy@1 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <0x1>;
> > + interrupt-parent = <&gpio2>;
> > + interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
> > + enet-phy-lane-no-swap;
> > + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
> > + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
> > + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> > + };
> > +
> > + ethphy2: ethernet-phy@8 {
> > + compatible = "ethernet-phy-ieee802.3-c45";
> > + reg = <0x8>;
> > + max-speed = <10000>; /* 10Gbit/s */
> > + status = "disabled";
> > + };
> > +};
> > +
> > +&pcie0 {
> > + reset-gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
> > + vpcie-supply = <®_vdd_3v3>;
> > + status = "okay";
> > +};
> > +
> > +&pcie1 {
> > + reset-gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
> > + vpcie-supply = <®_vdd_3v3>;
> > + status = "okay";
> > +};
> > +
> > +&rv3028 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_rtc>;
> > + interrupt-parent = <&gpio2>;
> > + interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
> > + aux-voltage-chargeable = <1>;
> > + wakeup-source;
> > + trickle-resistor-ohms = <3000>;
> > +};
> > +
> > +&scmi_iomuxc {
> > + pinctrl_lpuart2: lpuart2grp { /* FPSC proprietary */
> > + fsl,pins = <
> > + IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x3
> > 1e
> > + IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x3
> > 1e
> > + >;
> > + };
> > +
> > + pinctrl_lvds0: lvds0grp {
> > + fsl,pins = <
> > + IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_rtc: rtcgrp {
> > + fsl,pins = <
> > + IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_tpm4: tpm4grp {
> > + fsl,pins = <
> > + IMX95_PAD_GPIO_IO21__TPM4_CH1 0x51e
> > + >;
> > + };
> > +};
> > +
> > +&tpm4 {
> > + pinctrl-0 = <&pinctrl_tpm4>;
> > + pinctrl-names = "default";
> > +};
> > +
> > +&usb3 {
> > + fsl,over-current-active-low;
> > + fsl,power-active-low;
> > + status = "okay";
> > +};
> > +
> > +&usb3_phy {
> > + vbus-supply = <®_vdd_5v0>;
> > + status = "okay";
> > +};
> > +
> > +&usb3_dwc3 {
>
> In order of alphabet, usb3_dwc3 should go before usb3_phy, right?
Yes, should be.
>
> > + dr_mode = "peripheral";
> > + status = "okay";
> > +};
> > +
> > +/* uSD Card */
> > +&usdhc2 {
> > + status = "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi
> > b/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi
> > new file mode 100644
> > index 000000000000..0e3727d93df0
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi
> > @@ -0,0 +1,656 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright 2025 PHYTEC Messtechnik GmbH
> > + */
> > +
> > +#include <dt-bindings/net/ti-dp83867.h>
> > +#include "imx95.dtsi"
> > +
> > +/ {
> > + model = "PHYTEC phyCORE-i.MX95 FPSC";
> > + compatible = "phytec,imx95-phycore-fpsc", "fsl,imx95";
> > +
> > + aliases {
> > + ethernet1 = &enetc_port1;
> > + rtc0 = &rv3028;
> > + rtc1 = &scmi_bbm;
> > + i2c1 = &lpi2c2;
> > + i2c2 = &lpi2c5;
> > + i2c3 = &lpi2c3;
> > + i2c4 = &lpi2c4;
> > + i2c5 = &lpi2c1;
>
> Sort them please.
Will do
>
> > + };
> > +
> > + memory@...00000 {
> > + device_type = "memory";
> > + reg = <0x00000000 0x80000000 0x00000001 0x00000000>;
> > + };
> > +
> > + reg_nvcc_aon: regulator-nvcc-aon {
> > + compatible = "regulator-fixed";
> > + regulator-always-on;
> > + regulator-boot-on;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-name = "VDD_IO";
> > + };
> > +
> > + reg_usdhc2_vmmc: regulator-usdhc2 {
> > + compatible = "regulator-fixed";
> > + off-on-delay-us = <12000>;
> > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> > + pinctrl-names = "default";
> > + regulator-max-microvolt = <3300000>;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-name = "VDDSW_SD2";
> > + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + };
> > +
> > + reserved-memory {
> > + ranges;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + linux,cma {
> > + compatible = "shared-dma-pool";
> > + alloc-ranges = <0 0x80000000 0 0x7f000000>;
> > + reusable;
> > + size = <0 0x3c000000>;
> > + linux,cma-default;
> > + };
> > + };
> > +};
> > +
> > +&enetc_port0 { /* FPSC RGMII2 */
> > + phy-mode = "rgmii-id";
> > + pinctrl-0 = <&pinctrl_enetc0>;
> > + pinctrl-names = "default";
> > +};
> > +
> > +&enetc_port1 {
> > + phy-handle = <ðphy1>;
> > + phy-mode = "rgmii-id";
> > + pinctrl-0 = <&pinctrl_enetc1>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +};
> > +
> > +&flexcan1 { /* FPSC CAN1 */
> > + pinctrl-0 = <&pinctrl_flexcan1>;
> > + pinctrl-names = "default";
> > +};
> > +
> > +&flexcan2 { /* FPSC CAN2 */
> > + pinctrl-0 = <&pinctrl_flexcan2>;
> > + pinctrl-names = "default";
> > +};
> > +
> > +&flexspi1 { /* FPSC QSPI */
> > + pinctrl-0 = <&pinctrl_flexspi>;
> > + pinctrl-names = "default";
> > +};
> > +
> > +&gpio1 { /* FPSC GPIO */
> > + gpio-line-names = "", "", "", "", "GPIO2",
> > + "GPIO1", "", "", "", "",
> > + "PCIE1_nPERST", "USB1_PWR_EN", "GPIO3",
> > "USB2_PWR_EN", "PCIE2_nPERST";
> > + pinctrl-0 = <&pinctrl_gpio1>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +};
> > +
> > +&gpio2 { /* FPSC GPIO */
> > + gpio-line-names = "", "", "", "", "",
> > + "", "", "", "", "",
> > + "", "", "", "", "",
> > + "", "RGMII2_nINT", "GPIO4";
> > + pinctrl-0 = <&pinctrl_gpio2>;
> > + pinctrl-names = "default";
> > +};
> > +
> > +&gpio3 {
> > + gpio-line-names = "", "", "", "", "",
> > + "", "", "SD2_RESET_B";
> > +};
> > +
> > +&gpio4 {
> > + gpio-line-names = "ENET2_nINT";
> > +};
> > +
> > +&gpio5 {
> > + gpio-line-names = "", "", "", "", "",
> > + "", "", "", "", "",
> > + "", "", "", "USB1_OC", "USB2_OC";
> > +};
> > +
> > +&lpi2c1 { /* FPSC I2C5 */
> > + clock-frequency = <400000>;
> > + pinctrl-0 = <&pinctrl_lpi2c1>;
> > + pinctrl-names = "default";
> > + status = "okay";
> > +
> > + /* User EEPROM */
> > + eeprom@50 {
> > + compatible = "st,24c32", "atmel,24c32";
> > + reg = <0x50>;
> > + pagesize = <32>;
> > + vcc-supply = <®_nvcc_aon>;
> > + };
> > +
> > + /* Factory EEPROM */
> > + eeprom@51 {
> > + compatible = "st,24c32", "atmel,24c32";
> > + reg = <0x51>;
> > + pagesize = <32>;
> > + vcc-supply = <®_nvcc_aon>;
> > + };
> > +
> > + /* User EEPROM ID page */
> > + eeprom@58 {
> > + compatible = "st,24c32", "atmel,24c32";
> > + reg = <0x58>;
> > + pagesize = <32>;
> > + vcc-supply = <®_nvcc_aon>;
> > + };
> > +
> > + rv3028: rtc@52 {
>
> We usually sort I2C devices in order of slave address.
thanks,
Yannic
>
> Shawn
>
> >
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