linux-kernel - Re: [PATCH net-next 2/2] net: mdio-mux: Add MDIO mux driver for Sophgo CV1800 SoCs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <m3rqdpoztgbdocm2yx5ajcnfk7p7b2sifp6fibj3htsmw53mbl@icnaj6xndnjf>
Date: Thu, 12 Jun 2025 08:33:15 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Andrew Lunn <andrew@...n.ch>, Inochi Amaoto <inochiama@...il.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>, 
	"David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Chen Wang <unicorn_wang@...look.com>, Heiner Kallweit <hkallweit1@...il.com>, 
	Russell King <linux@...linux.org.uk>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Alexandre Ghiti <alex@...ti.fr>, netdev@...r.kernel.org, devicetree@...r.kernel.org, 
	sophgo@...ts.linux.dev, linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, 
	Yixun Lan <dlan@...too.org>, Longbin Li <looong.bin@...il.com>
Subject: Re: [PATCH net-next 2/2] net: mdio-mux: Add MDIO mux driver for
 Sophgo CV1800 SoCs

On Wed, Jun 11, 2025 at 06:13:00PM +0200, Andrew Lunn wrote:
> On Wed, Jun 11, 2025 at 04:02:00PM +0800, Inochi Amaoto wrote:
> > Add device driver for the mux driver for Sophgo CV18XX/SG200X
> > series SoCs.
> > 
> > @@ -0,0 +1,119 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Sophgo CV1800 MDIO multiplexer driver
> > + *
> > + * Copyright (C) 2025 Inochi Amaoto <inochiama@...il.com>
> > + */
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/bits.h>
> > +#include <linux/delay.h>
> > +#include <linux/clk.h>
> > +#include <linux/io.h>
> > +#include <linux/mdio-mux.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +
> > +#define EPHY_PAGE_SELECT		0x07c
> > +#define EPHY_CTRL			0x800
> > +#define EPHY_REG_SELECT			0x804
> > +
> > +#define EPHY_PAGE_SELECT_SRC		GENMASK(12, 8)
> > +
> > +#define EPHY_CTRL_ANALOG_SHUTDOWN	BIT(0)
> > +#define EPHY_CTRL_USE_EXTPHY		BIT(7)
> > +#define EPHY_CTRL_PHYMODE		BIT(8)
> > +#define EPHY_CTRL_PHYMODE_SMI_RMII	1
> > +#define EPHY_CTRL_EXTPHY_ID		GENMASK(15, 11)
> 
> There are a lot of defines here which are not used, but as far as i
> see, there is one 8bit register, where bit 7 controls the mux.
> 

You are true. Only bit 7 control the mux.

> It looks like you can throw this driver away and just use
> mdio-mux-mmioreg.c. This is from the binding documentation with a few
> tweaks:
> 
>    mdio-mux@...9000 {
>         compatible = "mdio-mux-mmioreg", "mdio-mux";
>         mdio-parent-bus = <&xmdio0>;
>         #address-cells = <1>;
>         #size-cells = <0>;
>         reg = <0x3009000 1>;
>         mux-mask = <128>;
> 
>         mdio@0 {
>             reg = <0>;
>             #address-cells = <1>;
>             #size-cells = <0>;
> 
>             phy_xgmii_slot1: ethernet-phy@4 {
>                 compatible = "ethernet-phy-ieee802.3-c45";
>                 reg = <4>;
>             };
>         };
> 
>         mdio@128 {
>             reg = <128>;
>             #address-cells = <1>;
>             #size-cells = <0>;
> 
>             ethernet-phy@4 {
>                 compatible = "ethernet-phy-ieee802.3-c45";
>                 reg = <4>;
>             };
>         };
>     };
> 

It is good for me to use this. I will have a try. Thanks.

Regards,
Inochi