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Message-ID: <CALE0LRsdsTU-NLN4fgh2c8qnS-pPP1BDJvjnvsSOnud8amk3=A@mail.gmail.com>
Date: Thu, 12 Jun 2025 10:48:20 +0200
From: Enric Balletbo i Serra <eballetb@...hat.com>
To: Roger Quadros <rogerq@...nel.org>
Cc: Siddharth Vadapalli <s-vadapalli@...com>, vkoul@...nel.org, kishon@...nel.org,
sjakhade@...ence.com, thomas.richard@...tlin.com,
christophe.jaillet@...adoo.fr, u.kleine-koenig@...libre.com,
linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, srk@...com
Subject: Re: [PATCH v3 1/2] phy: cadence-torrent: Add PCIe multilink
configuration for 100 MHz refclk
Hi all,
On Thu, Jan 9, 2025 at 5:35 PM Roger Quadros <rogerq@...nel.org> wrote:
>
>
>
> On 09/01/2025 14:16, Siddharth Vadapalli wrote:
> > From: Swapnil Jakhade <sjakhade@...ence.com>
> >
> > Add register sequences to support PCIe multilink configuration for 100MHz
> > reference clock. Maximum two PCIe links are supported.
> >
> > Signed-off-by: Swapnil Jakhade <sjakhade@...ence.com>
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
>
> Reviewed-by: Roger Quadros <rogerq@...nel.org>
>
These patches seem good and have been reviewed but look stalled here.
There is any chance to rebase it on top of the mainline?
Thanks,
Enric
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