linux-kernel - Re: [PATCH v6 08/17] drm/msm/dsi/phy: Fix reading zero as PLL rates when unprepared

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Message-ID: <dbcfcb3c-0cba-45f6-aaed-b79494d96cde@linaro.org>
Date: Fri, 13 Jun 2025 16:02:30 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Cc: Abhinav Kumar <quic_abhinavk@...cinc.com>, Sean Paul <sean@...rly.run>,
 Marijn Suijten <marijn.suijten@...ainline.org>,
 David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
 Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
 Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>,
 Krishna Manikandan <quic_mkrishn@...cinc.com>,
 Jonathan Marek <jonathan@...ek.ca>, Kuogee Hsieh <quic_khsieh@...cinc.com>,
 Neil Armstrong <neil.armstrong@...aro.org>,
 Dmitry Baryshkov <lumag@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Rob Clark <robin.clark@....qualcomm.com>,
 linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
 freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
 Abel Vesa <abel.vesa@...aro.org>, Srinivas Kandagatla <srini@...nel.org>
Subject: Re: [PATCH v6 08/17] drm/msm/dsi/phy: Fix reading zero as PLL rates
 when unprepared

On 13/06/2025 15:55, Dmitry Baryshkov wrote:
>>  
>> @@ -361,24 +373,47 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
>>  
>>  static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
>>  {
>> +	unsigned long flags;
>>  	u32 data;
>>  
>> +	spin_lock_irqsave(&pll->pll_enable_lock, flags);
>> +	--pll->pll_enable_cnt;
>> +	if (pll->pll_enable_cnt < 0) {
>> +		spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
>> +		DRM_DEV_ERROR_RATELIMITED(&pll->phy->pdev->dev,
>> +					  "bug: imbalance in disabling PLL bias\n");
>> +		return;
>> +	} else if (pll->pll_enable_cnt > 0) {
>> +		spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
>> +		return;
>> +	} /* else: == 0 */
>> +
>>  	data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>>  	data &= ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
>>  	writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
>>  	writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>> +	spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
>>  	ndelay(250);
> 
> What is this ndelay protecting? Is is to let the hardware to wind down
> correctly? I'm worried about dsi_pll_disable_pll_bias() beng followed up
> by dsi_pll_enable_pll_bias() in another thread, which would mean that
> corresponding writes to the REG_DSI_7nm_PHY_CMN_CTRL_0 can come up
> without any delay between them.
> 

Great question, but why do you ask me? The code was there already and
MSM DRM drivers are not something I know and could provide context about.


Best regards,
Krzysztof