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Message-ID: <c93b8a59-9466-4d2f-8141-81142f5ead8c@zytor.com>
Date: Fri, 13 Jun 2025 16:22:57 -0700
From: Xin Li <xin@...or.com>
To: Sohil Mehta <sohil.mehta@...el.com>, linux-kernel@...r.kernel.org,
kvm@...r.kernel.org
Cc: tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com,
seanjc@...gle.com, pbonzini@...hat.com, peterz@...radead.org,
brgerst@...il.com, tony.luck@...el.com, fenghuay@...dia.com
Subject: Re: [PATCH v1 0/3] x86/traps: Fix DR6/DR7 inintialization
On 6/13/2025 3:43 PM, Sohil Mehta wrote:
> On 6/13/2025 12:01 AM, Xin Li (Intel) wrote:
>
>>
>> Xin Li (Intel) (3):
>> x86/traps: Move DR7_RESET_VALUE to <uapi/asm/debugreg.h>
>> x86/traps: Initialize DR7 by writing its architectural reset value
>> x86/traps: Initialize DR6 by writing its architectural reset value
>>
>
> The patches fix the false bus_lock warning that I was observing with the
> infinite sigtrap selftest.
>
> Tested-by: Sohil Mehta <sohil.mehta@...el.com>
>
> I'll try it out again once you send the updated version.
Thank you very much!
>
> In future, should we incorporate a #DB (or bus_lock) specific selftest
> to detect such DR6/7 initialization issues?
I cant think of how to tests it. Any suggestion about a new test?
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