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Message-ID: <9D33DFBA-FE08-47B3-9663-7252B943F595@zytor.com>
Date: Fri, 13 Jun 2025 20:38:02 -0700
From: "H. Peter Anvin" <hpa@...or.com>
To: Xin Li <xin@...or.com>, Sohil Mehta <sohil.mehta@...el.com>,
        linux-kernel@...r.kernel.org, kvm@...r.kernel.org
CC: tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
        dave.hansen@...ux.intel.com, x86@...nel.org, seanjc@...gle.com,
        pbonzini@...hat.com, peterz@...radead.org, brgerst@...il.com,
        tony.luck@...el.com, fenghuay@...dia.com
Subject: Re: [PATCH v1 0/3] x86/traps: Fix DR6/DR7 inintialization

On June 13, 2025 4:22:57 PM PDT, Xin Li <xin@...or.com> wrote:
>On 6/13/2025 3:43 PM, Sohil Mehta wrote:
>> On 6/13/2025 12:01 AM, Xin Li (Intel) wrote:
>> 
>>> 
>>> Xin Li (Intel) (3):
>>>    x86/traps: Move DR7_RESET_VALUE to <uapi/asm/debugreg.h>
>>>    x86/traps: Initialize DR7 by writing its architectural reset value
>>>    x86/traps: Initialize DR6 by writing its architectural reset value
>>> 
>> 
>> The patches fix the false bus_lock warning that I was observing with the
>> infinite sigtrap selftest.
>> 
>> Tested-by: Sohil Mehta <sohil.mehta@...el.com>
>> 
>> I'll try it out again once you send the updated version.
>
>Thank you very much!
>
>> 
>> In future, should we incorporate a #DB (or bus_lock) specific selftest
>> to detect such DR6/7 initialization issues?
>
>
>I cant think of how to tests it.  Any suggestion about a new test?
>

You would have to map some memory uncached.

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