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Message-ID: <8e52fe1c-0c06-4e19-8552-ad3985ef8818@linaro.org>
Date: Fri, 13 Jun 2025 11:09:10 +0200
From: neil.armstrong@...aro.org
To: Pritam Manohar Sutar <pritam.sutar@...sung.com>, vkoul@...nel.org,
kishon@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
alim.akhtar@...sung.com, andre.draszik@...aro.org, peter.griffin@...aro.org,
kauschluss@...root.org, ivo.ivanov.ivanov1@...il.com,
m.szyprowski@...sung.com, s.nawrocki@...sung.com
Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, rosa.pila@...sung.com,
dev.tailor@...sung.com, faraz.ata@...sung.com, muhammed.ali@...sung.com,
selvarasu.g@...sung.com
Subject: Re: [PATCH v3 2/9] phy: exyons5-usbdrd: support HS phy for
ExynosAutov920
Hi,
s/exyons5/exynos5/ in subject
On 13/06/2025 07:56, Pritam Manohar Sutar wrote:
> This SoC has a single USB 3.1 DRD combo phy that supports both
> UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers
> those only support the UTMI+ (HS) interface.
>
> Support only UTMI+ port for this SoC which is very similar to what
> the existing Exynos850 supports.
>
> The combo phy support is out of scope of this commit.
>
> Add required change in phy driver to support HS phy for this SoC.
>
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@...sung.com>
> ---
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index 917a76d584f0..15965b4c6f78 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -2025,6 +2025,28 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
> .n_regulators = ARRAY_SIZE(exynos5_regulator_names),
> };
>
> +static const struct phy_ops exynosautov920_usbdrd_phy_ops = {
> + .init = exynos850_usbdrd_phy_init,
> + .exit = exynos850_usbdrd_phy_exit,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] = {
> + {
> + .id = EXYNOS5_DRDPHY_UTMI,
> + .phy_init = exynos850_usbdrd_utmi_init,
> + },
> +};
> +
> +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = {
> + .phy_cfg = phy_cfg_exynosautov920,
> + .phy_ops = &exynosautov920_usbdrd_phy_ops,
> + .clk_names = exynos5_clk_names,
> + .n_clks = ARRAY_SIZE(exynos5_clk_names),
> + .core_clk_names = exynos5_core_clk_names,
> + .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
> +};
> +
> static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = {
> {
> .id = EXYNOS5_DRDPHY_UTMI,
> @@ -2228,6 +2250,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
> }, {
> .compatible = "samsung,exynos850-usbdrd-phy",
> .data = &exynos850_usbdrd_phy
> + }, {
> + .compatible = "samsung,exynosautov920-usbdrd-phy",
> + .data = &exynosautov920_usbdrd_phy
> },
> { },
> };
Looks fine, with the subject fix:
Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>
Thanks,
Neil
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