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Message-ID: <d6031204-9bb5-4b0f-adf9-109b305e89e2@linaro.org>
Date: Fri, 13 Jun 2025 11:11:14 +0200
From: neil.armstrong@...aro.org
To: Pritam Manohar Sutar <pritam.sutar@...sung.com>, vkoul@...nel.org,
kishon@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
alim.akhtar@...sung.com, andre.draszik@...aro.org, peter.griffin@...aro.org,
kauschluss@...root.org, ivo.ivanov.ivanov1@...il.com,
m.szyprowski@...sung.com, s.nawrocki@...sung.com
Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, rosa.pila@...sung.com,
dev.tailor@...sung.com, faraz.ata@...sung.com, muhammed.ali@...sung.com,
selvarasu.g@...sung.com
Subject: Re: [PATCH v3 5/9] phy: exyons5-usbdrd: support HS combo phy for
ExynosAutov920
On 13/06/2025 07:56, Pritam Manohar Sutar wrote:
> This SoC has a single USB 3.1 DRD combo phy that supports both
> UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers
> those only support the UTMI+ (HS) interface.
>
> Support UTMI+ combo phy for this SoC which is somewhat simmilar to
> what the existing Exynos850 support does. The difference is that
> some register offsets and bit fields are defferent from Exynos850.
>
> Add required change in phy driver to support combo HS phy for this SoC.
>
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@...sung.com>
> ---
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 202 +++++++++++++++++++++++
> 1 file changed, 202 insertions(+)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index 15965b4c6f78..ac7bc1d1afd2 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -41,6 +41,13 @@
> #define EXYNOS2200_CLKRST_LINK_PCLK_SEL BIT(1)
>
> #define EXYNOS2200_DRD_UTMI 0x10
> +
> +/* ExynosAutov920 bits */
> +#define UTMICTL_FORCE_UTMI_SUSPEND BIT(13)
> +#define UTMICTL_FORCE_UTMI_SLEEP BIT(12)
> +#define UTMICTL_FORCE_DPPULLDOWN BIT(9)
> +#define UTMICTL_FORCE_DMPULLDOWN BIT(8)
> +
> #define EXYNOS2200_UTMI_FORCE_VBUSVALID BIT(1)
> #define EXYNOS2200_UTMI_FORCE_BVALID BIT(0)
>
> @@ -250,6 +257,22 @@
> #define EXYNOS850_DRD_HSP_TEST 0x5c
> #define HSP_TEST_SIDDQ BIT(24)
>
> +#define EXYNOSAUTOV920_DRD_HSP_CLKRST 0x100
> +#define HSPCLKRST_PHY20_SW_PORTRESET BIT(3)
> +#define HSPCLKRST_PHY20_SW_POR BIT(1)
> +#define HSPCLKRST_PHY20_SW_POR_SEL BIT(0)
> +
> +#define EXYNOSAUTOV920_DRD_HSPCTL 0x104
> +#define HSPCTRL_VBUSVLDEXTSEL BIT(13)
> +#define HSPCTRL_VBUSVLDEXT BIT(12)
> +#define HSPCTRL_EN_UTMISUSPEND BIT(9)
> +#define HSPCTRL_COMMONONN BIT(8)
> +
> +#define EXYNOSAUTOV920_DRD_HSP_TEST 0x10c
> +
> +#define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110
> +#define HSPPLLTUNE_FSEL GENMASK(18, 16)
> +
> /* Exynos9 - GS101 */
> #define EXYNOS850_DRD_SECPMACTL 0x48
> #define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12)
> @@ -2025,6 +2048,182 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
> .n_regulators = ARRAY_SIZE(exynos5_regulator_names),
> };
>
> +static void
> +exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
> +{
> + void __iomem *reg_phy = phy_drd->reg_phy;
> + u32 reg;
> +
> + /*
> + * Disable HWACG (hardware auto clock gating control). This
> + * forces QACTIVE signal in Q-Channel interface to HIGH level,
> + * to make sure the PHY clock is not gated by the hardware.
> + */
> + reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL);
> + reg |= LINKCTRL_FORCE_QACT;
> + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL);
> +
> + /* De-assert link reset */
> + reg = readl(reg_phy + EXYNOS2200_DRD_CLKRST);
> + reg &= ~CLKRST_LINK_SW_RST;
> + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST);
> +
> + /* Set PHY POR High */
> + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST);
> + reg |= HSPCLKRST_PHY20_SW_POR | HSPCLKRST_PHY20_SW_POR_SEL;
> + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST);
> +
> + /* Enable UTMI+ */
> + reg = readl(reg_phy + EXYNOS2200_DRD_UTMI);
> + reg &= ~(UTMICTL_FORCE_UTMI_SUSPEND | UTMICTL_FORCE_UTMI_SLEEP |
> + UTMICTL_FORCE_DPPULLDOWN | UTMICTL_FORCE_DMPULLDOWN);
> + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI);
> +
> + /* set phy clock & control HS phy */
> + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSPCTL);
> + reg |= HSPCTRL_EN_UTMISUSPEND | HSPCTRL_COMMONONN;
> + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL);
> +
> + usleep_range(100, 105);
> +
> + /* Set VBUS Valid and DP-Pull up control by VBUS pad usage */
> + reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL);
> + reg |= FIELD_PREP_CONST(LINKCTRL_BUS_FILTER_BYPASS, 0xf);
> + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL);
> +
> + reg = readl(reg_phy + EXYNOS2200_DRD_UTMI);
> + reg |= EXYNOS2200_UTMI_FORCE_VBUSVALID | EXYNOS2200_UTMI_FORCE_BVALID;
> + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI);
> +
> + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSPCTL);
> + reg |= HSPCTRL_VBUSVLDEXTSEL | HSPCTRL_VBUSVLDEXT;
> + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL);
> +
> + /* Setting FSEL for refference clock */
> + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE);
> + reg &= ~HSPPLLTUNE_FSEL;
> + switch (phy_drd->extrefclk) {
> + case EXYNOS5_FSEL_50MHZ:
> + reg |= FIELD_PREP(HSPPLLTUNE_FSEL, 7);
> + break;
> + case EXYNOS5_FSEL_26MHZ:
> + reg |= FIELD_PREP(HSPPLLTUNE_FSEL, 6);
> + break;
> + case EXYNOS5_FSEL_24MHZ:
> + reg |= FIELD_PREP(HSPPLLTUNE_FSEL, 2);
> + break;
> + case EXYNOS5_FSEL_20MHZ:
> + reg |= FIELD_PREP(HSPPLLTUNE_FSEL, 1);
> + break;
> + case EXYNOS5_FSEL_19MHZ2:
> + reg |= FIELD_PREP(HSPPLLTUNE_FSEL, 0);
> + break;
> + default:
> + dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",
> + phy_drd->extrefclk);
> + break;
> + }
> + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE);
> +
> + /* Enable PHY Power Mode */
> + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST);
> + reg &= ~HSP_TEST_SIDDQ;
> + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST);
> +
> + /* before POR low, 10us delay is needed to Finish PHY reset */
> + usleep_range(10, 15);
> +
> + /* Set PHY POR Low */
> + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST);
> + reg |= HSPCLKRST_PHY20_SW_POR_SEL;
> + reg &= ~(HSPCLKRST_PHY20_SW_POR | HSPCLKRST_PHY20_SW_PORTRESET);
> + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST);
> +
> + /* after POR low and delay 75us, PHYCLOCK is guaranteed. */
> + usleep_range(75, 80);
> +
> + /* force pipe3 signal for link */
> + reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL);
> + reg |= LINKCTRL_FORCE_PIPE_EN;
> + reg &= ~LINKCTRL_FORCE_PHYSTATUS;
> + reg |= LINKCTRL_FORCE_RXELECIDLE;
> + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL);
> +}
> +
> +static void
> +exynosautov920_usbdrd_hsphy_disable(struct exynos5_usbdrd_phy *phy_drd)
> +{
> + u32 reg;
> + void __iomem *reg_phy = phy_drd->reg_phy;
> +
> + /* set phy clock & control HS phy */
> + reg = readl(reg_phy + EXYNOS2200_DRD_UTMI);
> + reg |= UTMICTL_FORCE_UTMI_SUSPEND | UTMICTL_FORCE_UTMI_SLEEP;
> + reg &= ~(UTMICTL_FORCE_DPPULLDOWN | UTMICTL_FORCE_DMPULLDOWN);
> + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI);
> +
> + /* Disable PHY Power Mode */
> + reg = readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST);
> + reg |= HSP_TEST_SIDDQ;
> + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST);
> +
> + /* clear force q-channel */
> + reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL);
> + reg &= ~LINKCTRL_FORCE_QACT;
> + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL);
> +
> + /* link sw reset is need for USB_DP/DM high-z in host mode */
> + reg = readl(reg_phy + EXYNOS2200_DRD_CLKRST);
> + reg |= CLKRST_LINK_SW_RST;
> + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST);
> +}
> +
> +static int exynosautov920_usbdrd_phy_init(struct phy *phy)
> +{
> + return exynos850_usbdrd_phy_init(phy);
> +}
> +
> +static int exynosautov920_usbdrd_phy_exit(struct phy *phy)
> +{
> + struct phy_usb_instance *inst = phy_get_drvdata(phy);
> + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> + int ret = 0;
> +
> + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
> + if (ret)
> + return ret;
> +
> + if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
> + exynosautov920_usbdrd_hsphy_disable(phy_drd);
> +
> + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
> +
> + return 0;
> +}
> +
> +static const struct phy_ops exynosautov920_usb31drd_phy_ops = {
> + .init = exynosautov920_usbdrd_phy_init,
> + .exit = exynosautov920_usbdrd_phy_exit,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct
> +exynos5_usbdrd_phy_config usbdrd_hsphy_cfg_exynosautov920[] = {
> + {
> + .id = EXYNOS5_DRDPHY_UTMI,
> + .phy_init = exynosautov920_usbdrd_utmi_init,
> + },
> +};
> +
> +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_hsphy = {
> + .phy_cfg = usbdrd_hsphy_cfg_exynosautov920,
> + .phy_ops = &exynosautov920_usb31drd_phy_ops,
> + .clk_names = exynos5_clk_names,
> + .n_clks = ARRAY_SIZE(exynos5_clk_names),
> + .core_clk_names = exynos5_core_clk_names,
> + .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
> +};
> +
> static const struct phy_ops exynosautov920_usbdrd_phy_ops = {
> .init = exynos850_usbdrd_phy_init,
> .exit = exynos850_usbdrd_phy_exit,
> @@ -2250,6 +2449,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
> }, {
> .compatible = "samsung,exynos850-usbdrd-phy",
> .data = &exynos850_usbdrd_phy
> + }, {
> + .compatible = "samsung,exynosautov920-usbdrd-hsphy",
> + .data = &exynosautov920_usbdrd_hsphy
> }, {
> .compatible = "samsung,exynosautov920-usbdrd-phy",
> .data = &exynosautov920_usbdrd_phy
With the subject fixed:
Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>
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