linux-kernel - [RESEND PATCH 0/2] Add SMMU-V3-PMCG and L2/L3 cache nodes in Agilex5 DTSI

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Message-ID: <20250616145006.1081013-1-adrianhoyin.ng@altera.com>
Date: Mon, 16 Jun 2025 22:50:04 +0800
From: adrianhoyin.ng@...era.com
To: dinguyen@...nel.org,
	robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Cc: adrianhoyin.ng@...era.com
Subject: [RESEND PATCH 0/2] Add SMMU-V3-PMCG and L2/L3 cache nodes in Agilex5 DTSI

From: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>

This patchset include the following changes:
-Add SMMU-V3-PMCG node for Agilex5
-Add L2 and L3 cache node for Agilex5

Adrian Ng Ho Yin (2):
  arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
  arm64: dts: socfpga: agilex5: Add L2 and L3 cache

 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 80 +++++++++++++++++++
 1 file changed, 80 insertions(+)

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2.49.GIT