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Message-ID: <20250616145006.1081013-3-adrianhoyin.ng@altera.com>
Date: Mon, 16 Jun 2025 22:50:06 +0800
From: adrianhoyin.ng@...era.com
To: dinguyen@...nel.org,
	robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Cc: adrianhoyin.ng@...era.com,
	Kah Jing Lee <kah.jing.lee@...el.com>,
	Matthew Gerlach <matthew.gerlach@...rera.com>
Subject: [RESEND PATCH 2/2] arm64: dts: socfpga: agilex5: Add L2 and L3 cache

From: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>

Add L2 and L3 cache to fix the cacheinfo warning "unable to detect cache hierarchy".

Signed-off-by: Kah Jing Lee <kah.jing.lee@...el.com>
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@...rera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 06920de87a41..a66c92578803 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -37,6 +37,7 @@ cpu0: cpu@0 {
 			reg = <0x0>;
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu@1 {
@@ -44,6 +45,7 @@ cpu1: cpu@1 {
 			reg = <0x100>;
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&L2>;
 		};
 
 		cpu2: cpu@2 {
@@ -51,6 +53,7 @@ cpu2: cpu@2 {
 			reg = <0x200>;
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&L2>;
 		};
 
 		cpu3: cpu@3 {
@@ -58,7 +61,22 @@ cpu3: cpu@3 {
 			reg = <0x300>;
 			device_type = "cpu";
 			enable-method = "psci";
+			next-level-cache = <&L2>;
 		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			next-level-cache = <&L3>;
+			cache-unified;
+		};
+
+		L3: l3-cache {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-unified;
+		};
+
 	};
 
 	psci {
-- 
2.49.GIT


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