linux-kernel - [PATCH] PCI: endpoint: Use common PCI host bridge APIs for finding the capabilities

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Message-Id: <20250616152515.966480-1-18255117159@163.com>
Date: Mon, 16 Jun 2025 23:25:15 +0800
From: Hans Zhang <18255117159@....com>
To: lpieralisi@...nel.org,
	kwilczynski@...nel.org,
	bhelgaas@...gle.com,
	jingoohan1@...il.com,
	mani@...nel.org
Cc: robh@...nel.org,
	ilpo.jarvinen@...ux.intel.com,
	linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Hans Zhang <18255117159@....com>
Subject: [PATCH] PCI: endpoint: Use common PCI host bridge APIs for finding the capabilities

Use the PCI core is now exposing generic macros for the host bridges to
search for the PCIe capabilities, make use of them in the DWC EP driver.

Signed-off-by: Hans Zhang <18255117159@....com>
---
- Submissions based on the following patches:
https://patchwork.kernel.org/project/linux-pci/patch/20250607161405.808585-1-18255117159@163.com/

Recently, I checked the code and found that there are still some areas that can be further optimized.
The above series of patches has been around for a long time, so I'm sending this one out for review
as a separate patch.
---
 .../pci/controller/dwc/pcie-designware-ep.c   | 39 +++++++------------
 1 file changed, 14 insertions(+), 25 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 0ae54a94809b..9f1880cc1925 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -69,37 +69,26 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
 }
 EXPORT_SYMBOL_GPL(dw_pcie_ep_reset_bar);
 
-static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no,
-				     u8 cap_ptr, u8 cap)
+static int dw_pcie_ep_read_cfg(void *priv, u8 func_no, int where, int size, u32 *val)
 {
-	u8 cap_id, next_cap_ptr;
-	u16 reg;
-
-	if (!cap_ptr)
-		return 0;
-
-	reg = dw_pcie_ep_readw_dbi(ep, func_no, cap_ptr);
-	cap_id = (reg & 0x00ff);
-
-	if (cap_id > PCI_CAP_ID_MAX)
-		return 0;
-
-	if (cap_id == cap)
-		return cap_ptr;
+	struct dw_pcie_ep *ep = priv;
+
+	if (size == 4)
+		*val = dw_pcie_ep_readl_dbi(ep, func_no, where);
+	else if (size == 2)
+		*val = dw_pcie_ep_readw_dbi(ep, func_no, where);
+	else if (size == 1)
+		*val = dw_pcie_ep_readb_dbi(ep, func_no, where);
+	else
+		return PCIBIOS_BAD_REGISTER_NUMBER;
 
-	next_cap_ptr = (reg & 0xff00) >> 8;
-	return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap);
+	return PCIBIOS_SUCCESSFUL;
 }
 
 static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8 cap)
 {
-	u8 next_cap_ptr;
-	u16 reg;
-
-	reg = dw_pcie_ep_readw_dbi(ep, func_no, PCI_CAPABILITY_LIST);
-	next_cap_ptr = (reg & 0x00ff);
-
-	return __dw_pcie_ep_find_next_cap(ep, func_no, next_cap_ptr, cap);
+	return PCI_FIND_NEXT_CAP_TTL(dw_pcie_ep_read_cfg, PCI_CAPABILITY_LIST,
+				     cap, ep, func_no);
 }
 
 /**

base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
-- 
2.25.1